Semiconductor device and manufacturing method thereof

ABSTRACT

It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers  13, 15  is formed on different layers with insulating film  14  sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers  16, 17  having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT  30  of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device having acircuit constituted of a thin film transistor (hereinafter, referred toas TFT) and manufacturing method thereof. More particularly, theinvention relates, for example, to an electrooptical device exemplifiedby a liquid crystal display panel and a light-emitting deviceexemplified by an electroluminescence display device and electronicapparatus on which electrooptical devices as described-above are mountedas component parts thereof.

[0002] In this specification, the term “semiconductor device” meansevery device that functions by using the semiconductor characteristics;i.e., electrooptical devices, light-emitting devices, semiconductorcircuits and electronic apparatuses are all included in thesemiconductor device.

[0003] Recently, a technique, in which a thin film transistor (TFT) isconstituted using a semiconductor thin film (approximately severalnm-several hundreds nm in thickness) having an insulated surface on asubstrate, has attracted attention. The thin film transistor has beenwidely applied to electronic devices such as IC, electrooptical deviceand so on; in particular, it is desired to develop the same as aswitching element for display device on various apparatuses.

[0004] Particularly, an active matrix type liquid crystal displaydevice, which is provided with switching element of TFT to each displaypixel disposed on a matrix, has been developed.

[0005] As for the active matrix type liquid crystal display device, adevelopment to extend the effective screen area in the pixel section isnow under progression. To enlarge the area of the effective screen area,it is necessary to reduce the area occupied by the TFT disposed in thepixel section as small as possible. Further, in order to reduce themanufacturing cost, a development to build a drive circuit on the samesubstrate along with the pixel section is also under progression. Whenthe drive circuit and the pixel section are formed on the samesubstrate, compared to the case that the drive circuit is mounted in amanner of TAB, there is a tendency that the area occupied by area otherthan the pixel area, which is called as frame rim area, become large. Itis also requested that, in order to reduce the frame rim area, the sizeof the circuit constituting the drive circuit should be formed furthersmaller in size.

[0006] Particularly, in an organic light emitting device (OLED), aplurality of TFTs, which are different from each other in function, forone pixel. Further, in the liquid crystal display device also, anattempt to form switching TFT and memory element such as SRAM or thelike in a pixel has been made. Furthermore, when the pixel section andthe drive circuit are formed on the same substrate, it is requested tominiaturize the same as small as possible. As described above, when aplurality of elements are formed within a limited area, a design, inwhich the elements are disposed on a plane, or a design, in which theelements are piled up, are conceivable. In the case that the elementsare disposed on a plane, since the required area allowed to occupy islimited, when the area is limited, a limitation resides therein. Also,in a design that the elements are piled up, for example, when two TFTsare piled up, the number of steps is increased simply by two times ormore resulting in a complication in the steps, an increase of cost, areduction of the throughput and a reduction of the yield.

[0007] As for designs of conventional techniques in which elements arepiled up; for example, Japanese Unexamined Patent ApplicationPublication No.10-93099 and Japanese Unexamined Patent ApplicationPublication No.10-93100 respectively disclose a structure in which anFET and a TFT are piled up on a semiconductor substrate. Also, inJapanese Unexamined Patent Application Publication No. 11-40772, astructure, in which TFTs are disposed being piled up and interposed byinsulating film on a bulk transistor, is disclosed. According to thesePublications, in any case, an FET or a bulk transistor is formed using asemiconductor substrate, and a TFT is simply formed thereon.

[0008] An object of the invention is, in order to promote the tendencytoward the foreseeable further compaction in each display pixel pitchaccompanying the tendency of higher precision (increase in pixel number)and miniaturization in electrooptical device exemplified by liquidcrystal display device, light-emitting device having OLED andsemiconductor device, to form a plurality of elements within a limitedarea and to integrate the same by compacting the area occupied by theelements.

SUMMARY OF THE INVENTION

[0009] The invention is characterized in that a plurality ofsemiconductor layers (semiconductor films having crystal structurerespectively) are disposed on the different layers respectively withinsulating films sandwiched therebetween so that a part the respectivelayers is overlapped with each other, and a plurality of elements, ofwhich functions are different from each other on the basis of therespective semiconductor layers, are formed and integrated tominiaturize the circuit size. The above-mentioned “element” means a thinfilm transistor (P-channel type TFT, N-channel type TFT), a memoryelement, a thin film diode, a photoelectric conversion element ofsilicon PIN junction or a silicon resistance element.

[0010] The constitution 1 of the invention disclosed in thespecification is:

[0011] a semiconductor device which comprises, on an insulated surfacethereof, a first element which has a first semiconductor layer formed ofa semiconductor film having crystal structure, an insulating film on thefirst semiconductor layer, and a second element which has a secondsemiconductor layer formed of a semiconductor film having crystalstructure on the insulating film, wherein, between the firstsemiconductor layer and the second semiconductor layer, the insulatingfilm only is included, a part of the first semiconductor layer isoverlapped with a part of the second semiconductor layer with theinsulating film sandwiched therebetween.

[0012] Typically, a double-layered semiconductor layer (typically,polysilicon film) is disposed on different layers with an insulatingfilm sandwiched therebetween, below the semiconductor layer of the lowerlayer of the double-layered semiconductor layer, a gate electrode isprovided to form an inversed stagger type TFT, while, above thesemiconductor layer of the upper layer thereof, a gate electrode isprovide to form a top gate type TFT. Further, an impurity element forimparting P-type to the upper semiconductor layer may be added, and theimpurity element for imparting N-type to the lower semiconductor layermay be added; thereby an N-channel type TFT and a P-channel type TFT canbe formed. By combining these TFTs, a CMOS circuit (inverter circuit,NAND circuit, AND circuit, NOR circuit, OR circuit, shift registercircuit, sampling circuit, D/A converter circuit, A/D converter circuit,latch circuit, buffer circuit or the like) can be constituted in an areasmaller than conventional area. The term “CMOS circuit” means a circuitthat has at least an N-channel type TFT and a P-channel type TFT.Additionally, by combining these CMOS circuits, a memory element such asSRAM, DRAM or the like or other element can be constituted. Accordingly,it is possible to miniaturize the area occupied by a drive circuithaving various circuits and elements, and since the area of frame rimbecome smaller; the entire size becomes more compact.

[0013] The constitution 2 of the invention disclosed in thespecification is, as shown with a typical example thereof in FIG. 1, aconstitution in which a P-channel type TFT is formed on an N-channeltype TFT, that is:

[0014] a semiconductor device which comprises a CMOS circuit disposed onan insulated surface, wherein

[0015] an N-channel type TFT having a first semiconductor layer as anactive layer, an insulating film on the first semiconductor layer and aP-channel type TFT having a second semiconductor layer as a active layeron the insulating film are connected complementally to each other,

[0016] between the first semiconductor layer and the secondsemiconductor layer, the insulating film only is included,

[0017] above the second semiconductor layer, a gate insulating film ofthe P-channel type TFT and a gate electrode are include,

[0018] below the first semiconductor layer, a gate insulating film ofthe N-channel type TFT and a gate electrode are include,

[0019] a part of the first semiconductor layer is overlapped with a partof the second semiconductor layer with the insulating film sandwichedtherebetween.

[0020] Further, when carrying out doping processing of the impurityelement for imparting conduction type using the gate electrode of topgate type TFT as a mask in a manner of self-aligning, it is possible toreduce the number of the masks, and it is possible to provide a top gatetype TFT and an inversed stagger type TFT that have the same channellength.

[0021] The constitution 3 of the invention disclosed in thespecification is a constitution, in which an N-channel type TFT isformed on a P-channel type TFT, that is:

[0022] a semiconductor device that comprises a CMOS circuit disposed onan insulated surface, wherein

[0023] an P-channel type TFT having a first semiconductor layer as anactive layer, an insulating film on the first semiconductor layer and aN-channel type TFT having a second semiconductor layer as a active layeron the insulating film are connected complementally to each other,

[0024] between the first semiconductor layer and the secondsemiconductor layer, the insulating film only is included,

[0025] over the second semiconductor layer, a gate insulating film ofthe N-channel type TFT and a gate electrode are include,

[0026] below the first semiconductor layer, a gate insulating film ofthe P-channel type TFT and a gate electrode,

[0027] a part of the first semiconductor layer is overlapped with a partof the second semiconductor layer with the insulating film sandwichedtherebetween.

[0028] According to the invention, in a light-emitting device having anOLED, it is possible to form a switching TFT and a current controllingTFT in a small area within a pixel. Accordingly, since it is possible tomake the area of an effective screen area larger, and further, to makeeach pixel size smaller, it is possible to provide a high preciselight-emitting device.

[0029] The constitution 4 of the invention disclosed in thespecification is:

[0030] a semiconductor device which comprises a OLED disposed on aninsulated surface, wherein

[0031] an N-channel type TFT having a first semiconductor layer as anactive layer, an insulating film on the first semiconductor layer and aP-channel type TFT having a second semiconductor layer as a active layeron the insulating film are included,

[0032] the P-channel type TFT is connected to the OLED,

[0033] between the first semiconductor layer and the secondsemiconductor layer, the insulating film only is included,

[0034] above the second semiconductor layer, a gate insulating film ofthe P-channel type TFT and a gate electrode are include,

[0035] below the first semiconductor layer, a gate insulating film ofthe N-channel type TFT and a gate electrode,

[0036] a part of the first semiconductor layer is overlapped with a partof the second semiconductor layer with the insulating film sandwichedtherebetween.

[0037] In this specification, every layer formed between the anode andthe cathode of the OLED is defined as “organic light-emitting layer”. Inparticular, the organic light-emitting layer includes a light-emittinglayer, a positive hole injection layer, an electron injection layer, apositive hole carrier layer, an electron carrier layer or the like.Basically, the OLED has such a structure that an anode, a light-emittinglayer and a cathode are built up in that order. In addition to thisstructure, there may be such structured that an anode, a positive holeinjection layer, a light-emitting layer and a cathode are built up inthat order; or, an anode, a positive hole injection layer, alight-emitting layer, an electron carrier layer and a cathode or thelike are built up in that order.

[0038] The OLED has a layer (hereinafter, referred to as organiclight-emitting layer) including an organic compound (organiclight-emitting material), from which luminescent (Electroluminescence)can be obtained by applying an electric field thereto, an anode and acathode. There are two modes of luminescence in organic compound; i.e.,light emission (fluorescence) obtained when the same returns from asinglet exiton state to a ground state, and light emission(phosphorescence) obtained when the same returns from a triplet exitonstate to a ground state. In the light-emitting device according to theinvention, any one or both of the above-described modes of luminescencemay be used.

[0039] Further, in liquid crystal display device also, owing to theinvention, since it is possible that a switching TFT and memory element(SRAM, DRAM or the like) comprised of an inverter circuit are formed ina small area on a pixel, and the effective screen area are made larger,and further, each pixel size is miniaturized, it is possible to providea high precise liquid crystal display device.

[0040] Furthermore, by adding the impurity element for imparting N-typeto both of the layers of a double-layered semiconductor, it is possibleto form two N-channel type TFTs (top gate type and inversed staggertype).

[0041] Still further, as a constitution different from theabove-described constitutions 1-4, it is not the case that one gateelectrode is provided to one semiconductor layer, but the case that onegate electrode is provided to two semiconductor layers. In that case,below the semiconductor layer of the lower layer, or above thesemiconductor layer of the upper layer in the layers of thedouble-layered semiconductor, the gate electrode is provided. Also, whenone gate electrode is provided to two semiconductor layers, and theimpurity element for imparting N-type or P-type to the semiconductorlayer of two layers, the threshold voltage varies depending on thethickness of the insulating film sandwiched between the layers of thedouble-layered semiconductor. Also, the impurity element for impartingP-type may be added to the semiconductor layer of the upper layer,while, the impurity element for imparting N-type may be added to thesemiconductor layer of the lower layer, thereby it is possible to formN-channel type TFT and P-channel type TFT respectively. Since a commongate electrode is provided, by carrying out doping of the impurityelement for imparting conduction type using the gate electrode as amask, it is possible to form the channel of the same length. Bycombining these TFTs, it is possible to constitute a CMOS circuit in asmaller area.

[0042] The constitution 5 of the invention disclosed in thisspecification is:

[0043] a semiconductor device which comprises a CMOS circuit disposed onan insulated surface, wherein

[0044] an N-channel type TFT having a first semiconductor layer as anactive layer, an insulating film on the first semiconductor layer and aP-channel type TFT having a second semiconductor layer as a active layeron the insulating film are connected complementally to each other,

[0045] between the first semiconductor layer and the secondsemiconductor layer, the insulating film only is included,

[0046] above the second semiconductor layer, a gate insulating film anda gate electrode are included,

[0047] the gate electrode of the N-channel type TFT and the P-channeltype TFT is the identical,

[0048] a part of the first semiconductor layer is overlapped with a partof the second semiconductor layer with the insulating film sandwichedtherebetween.

[0049] According to the above-described constitution 5, in alight-emitting device having an OLED, it is possible to form a switchingTFT and a current controlling TFT in a small area on one pixel. Further,according to the above-described constitution 5, in a liquid crystaldisplay device, it is possible to form a memory element (SRAM, DRAM orthe like) comprised of a switching TFT and an inverter circuit in asmall area of one pixel.

[0050] Further, in any one of the above-described constitutions 2-5, thefirst semiconductor layer and the second semiconductor layer aresemiconductor films having crystal structure.

[0051] In any one of the above-described constitutions 2-5, it ischaracterized in that the first semiconductor layer and the secondsemiconductor layer have at least a channel forming area, a source areaand a drain area respectively, the area where a part of the firstsemiconductor layer is overlapped with a part of the secondsemiconductor layer with an insulating film sandwiched therebetween isat least a channel forming area, and a source area or a drain area alsois overlapped with each other.

[0052] In this specification, the area, which is called as channelforming area (also, called as “channel”), is an area including a portionwhere carriers (electron/hole) flow. For example, in the case ofinversed stagger type TFT, a channel is formed adjacent to the boundarybetween the gate insulating film and the semiconductor film, where isabove the gate electrode. The entire area sandwiched between theinsulating film covering the semiconductor film including the areaadjacent to the boundary of the semiconductor film and the gateinsulating film is called as “channel forming area”.

[0053] Further, in any one of the above-described constitutions 2-5, itis characterized in that the channel length of the channel forming areain the first semiconductor layer and the channel length of the channelforming area in the second semiconductor layer are the same.

[0054] In Japanese Unexamined Patent Application Publication No.5-257169, a technique in which, in a liquid crystal display device, twoTFTs are formed by piling a inversed stagger type TFT and a stagger typeTFT; one is formed as an N-channel and the other is formed as aP-channel, is disclosed. However, according to the above-describedPublication, although two TFTs are formed, the source and the drain areformed commonly, and two TFTs function as a sole switching element; thesame is largely different from the invention. According to theinvention, a plurality of elements having different functionsrespectively is formed. Additionally, according to the above-describedPublication, since the TFTs are of amorphous silicon, it is difficult toform a CMOS circuit for the drive circuit, and further, the same are notsuitable as TFTs to be connected to the OLED.

[0055] As a constitution different from the above-describedconstitutions 1-5, a TFT may be such constituted that a plurality ofchannel forming areas are included therein by providing a gate electrodeto two semiconductor layers. In this case, connection electrodes forelectrically connecting the semiconductor layer of the upper layer andthe semiconductor layer of the lower layer are provided. Since a commongate electrode is provided, although it is possible to form the channellength so as to be the same, but since the distance from the gateelectrode, the same is different from conventional double gatestructure. Owing to this arrangement, it is possible to provide amulti-gate constitution in a small area without disposing a plurality ofgate electrodes. It is possible to form, for example, in a liquidcrystal display device, a switching TFT having a plurality of channelforming area in a small area on one pixel.

[0056] As an example is shown in FIG. 4, the constitution 6 of theinvention disclosed in this specification is:

[0057] a semiconductor device which comprises a TFT having a pluralityof channel forming areas disposed on an insulated surface, wherein

[0058] the TFT includes a first semiconductor layer and a secondsemiconductor layer as active layers,

[0059] the first semiconductor layer and the second semiconductor layerare electrically connected to each other via electrodes,

[0060] between the first semiconductor layer and the secondsemiconductor layer, an insulating film only is included,

[0061] on the second semiconductor layer, a gate insulating film of theTFT, and on the gate insulating film, a gate electrode are included,

[0062] in the second semiconductor layer, an area where is overlappedwith the gate electrode with the gate insulating film sandwichedtherebetween is a second channel forming area,

[0063] in the first semiconductor layer, an area where is overlappedwith the gate electrode with the gate insulating film, the secondchannel forming area and the insulating film sandwiched therebetween isa first channel forming area.

[0064] Also, in the above-described constitution 6, by providing a gateelectrode to two semiconductor layers, and carrying out doping ofimpurity element for imparting conduction type on a TFT, which has aplurality of channel forming areas, in a manner of self-aligning using acommon gate electrode as a mask, a multi-gate constitution having thesame channel length can be provided.

[0065] Furthermore, in the above-described constitution 6, when a TFThaving a plurality of channel forming areas is formed by providing agate electrode to two semiconductor layers, it is possible to form acapacitance using an insulating film sandwiched between the twosemiconductor layers as a dielectric.

[0066] In any one of the above-described constitutions 1-6, it ischaracterized in that the film thickness of the first semiconductorlayer is the same as that of the second semiconductor layer, or thinnerthan the film thickness of the second semiconductor layer.

[0067] Further, in any one of the above-described constitutions 1-6, thefilm thickness of the insulating film disposed between plurality ofsemiconductor layers is appropriately selectable within a range of 10nm-2 μm. Particularly, in the case that a plurality of differentelements is formed, by forming the film thickness of the insulating film200 nm or more, when a plurality of the respective elements, in whicheach of the semiconductor layers is formed as an active layer, isdriven, it is possible to prevent influences among the respectiveelements.

[0068] Furthermore, a several kinds of constitutions may be formed byappropriately combining the above-described constitutions 1-6 on thesame substrate.

[0069] The manufacturing method of a plurality of semiconductor layers,which is formed on different layers with insulating film sandwichedtherebetween, is one of characteristics of the invention, wherein, bymeans of irradiation processing of laser beam, crystallization of theplurality of semiconductor layers is carried out simultaneously.Accordingly, between the respective semiconductor layers, only theinsulating film is built up so that the laser beam is irradiated onevery semiconductor layer. In more particular, a laser beam isirradiated on a semiconductor film having amorphous structure on theupper layer to crystallize the same, and further, by allowing a part ofthe laser beam to pass through a semiconductor film having amorphousstructure on the upper layer, and further, through the insulating film,to irradiate the semiconductor film having amorphous structure on thelower layer to crystallize the same, and at the same time, to form aplurality of semiconductor layers, which is comprised of a semiconductorfilms having crystal structure. And an element or a plurality ofelements that has these pluralities of semiconductor layers is formed.

[0070] The constitution with respect to the manufacturing methoddisclose in this specification is:

[0071] a manufacturing method of semiconductor device, which comprises:

[0072] a first step for forming a first semiconductor film havingamorphous structure on an insulated surface,

[0073] a second step for forming an insulating film on the semiconductorfilm,

[0074] a third step for forming a second semiconductor film havingamorphous structure on the insulating film,

[0075] a fourth step for irradiating a laser beam to the firstsemiconductor film having amorphous structure and the secondsemiconductor film having amorphous structure to form the firstsemiconductor film having crystal structure and the second semiconductorfilm having crystal structure simultaneously.

[0076] The laser beam used in the invention is selectable from gas lasersuch as excimer laser, Ar laser, Kr laser or the like; solid-state lasersuch as YAG laser, YVO₄ laser, YLF laser, YAlO₃ laser, glass laser, rubylaser, alexandrite laser, Ti: sapphire laser or the like; and full-solidinfrared laser of semiconductor laser excitation. It is desired that thelaser is a large output laser having a wavelength range, which passesthrough a single layer semiconductor and is absorbed by a semiconductorlayer. FIG. 6A shows the transmittance with respect to an amorphoussilicon film of 55 nm in film thickness; FIG. 6B shows the reflectancethereof. FIG. 7A shows the transmittance with respect to a polysiliconfilm of 55 nm in film thickness, and FIG. 7B shows the reflectancethereof. In FIG. 6 and FIG. 7, at a wavelength, the sum of thetransmittance, the reflectance and the absorptance is 1.

[0077] Based on FIG. 6 and FIG. 7, as for the laser beam used in theinvention, light having a wavelength range of 400 nm-800 nm.

[0078] The mode of laser oscillation is selectable from continuousoscillation and pulse oscillation. Also, the configuration of the laserbeam in the irradiation area is selectable from line-like,rectangular-like and ellipse-like in configuration. To obtain a largesize crystal by crystallization of a semiconductor film having amorphousstructure, it is desired to use a solid-state laser capable ofcontinuous oscillation and to apply second harmonic-fourth harmonic inthe basic wave. As for the solid-state laser, a laser using a crystal ofYAG, YVO₄, YLF, YAlO₃ or the like doped with Cr, Nd, Er, Ho, Ce, Co, Tior Tm is applied to. The basic wave of the laser varies depending ondoping material, and laser beam having 1 μm or so in basic wave isobtained. The harmonic with respect to the basic wave can be obtained byusing a nonlinear optical element.

[0079] When the crystallizing is carried out by irradiating laser beamof continuous oscillation to the semiconductor film, which has amorphousstructure, it is possible that the solid-liquid phase boundary is heldto allow the crystal growing continuously in the scanning direction ofthe laser beam.

[0080] Since the energy given by the laser of continuous oscillation islarge, it is possible to crystallize the double-layered semiconductorlayer by one laser irradiation processing. If necessary, the laserirradiation processing may be repeated several times. Also, although thelaser beam incident the substrate is reflected at the surface of thesubstrate, since the laser beam is light having a high directivity andenergy density, a damper may be provided to absorb the reflected lightin order to prevent the reflected light from irradiating undesired area.According to the invention, it is possible to absorb the reflected lightat the surface of the substrate by the double-layered semiconductor,since almost every laser beam can be absorbed by providing adouble-layered or more semiconductor layer, particular damper may not beprovided. Furthermore, since it is also possible to absorb the reflectedlight of the semiconductor layer of the lower layer by carrying out theirradiation again to the semiconductor layer of the upper layer, it ispossible to irradiate the laser beam to the semiconductor layereffectively. Further, by repeating the reflection between thedouble-layered semiconductor layers and between the semiconductor layerand the substrate, it is possible to irradiate the laser beam to thesemiconductor layer effectively. Still further, when by providing ametal film having a high reflectance below the double-layeredsemiconductor layer, by repeating the reflection between thedouble-layered semiconductor layer, and between the semiconductor layerand the metal film, it is also possible to irradiate the laser beam tothe semiconductor layer effectively. According to the invention, thelaser beam, which has passed a single layer of the semiconductor layer,is used effectively. As described above, it is possible to give energyto the double-layered semiconductor layer effectively by means of alarge output laser. Further, it is possible to reduce the damages givenon the substrate or the like due to the irradiation of a large outputlaser.

[0081] Further, when the scanning is carried out while irradiating thelaser beam selectively, since it is possible to crystallize thedouble-layered semiconductor layer, it is possible to reduce the totalirradiation area resulting in an increased throughput.

[0082] Furthermore, when a full-solid infrared laser of semiconductorlaser excitation is used, the wavelength (1064 nm) of a full-solidinfrared laser beam may be reduced into a half using a green-conversionoptical crystal to generate a large output (100 W or more) green laserbeam (wavelength 532 nm).

[0083] Still further, a laser having a low transmittance with respect tothe amorphous silicon film, since almost every laser beam is absorbed bythe semiconductor layer of the upper layer, the state of the crystal ofthe semiconductor layer of the upper layer differs from that of thesemiconductor layer of the lower layer.

[0084] In the case that a TFT having a semiconductor layer of the upperlayer as the active layer may be different in characteristics from a TFThaving semiconductor layer of the lower layer as the active layer, thestate of the crystal of the semiconductor layer of the upper layer maybe different from that of the semiconductor layer of the lower layer.For example, if an enough ON/OFF ratio is obtained, and OFF-currentvalue is at least, 1×10⁻⁶(A) or less, the TFT used in CMOS circuit isusable. Further, in the case that the characteristics of one TFT isparticularly important, the energy of the laser beam, which is absorbedby the semiconductor film having first amorphous structure, may bedifferent from the energy of the laser beam, which is absorbed by thesemiconductor film having second amorphous structure.

[0085] When it is desired that the characteristics are the same betweenthe TFT having the semiconductor layer of the upper layer as the activelayer and the TFT having the semiconductor layer of the lower layer asthe active layer, in order to obtain the semiconductor layers havingsubstantially same crystalinity, it is preferred to adapt so that theenergies absorbed as the total become roughly the same to each other byaltering the film thickness of the double-layered semiconductor layer.For example, in two semiconductor layers, the upper layer may have athinner film thickness; while, the lower layer may have a thicker filmthickness. When the laser that passes through the upper layer is a half;i.e., the absorptance with respect to the semiconductor layer of theupper layer is 50%, it may be adapted so that the film thickness of thelower layer is approximately twice as the film thickness of the upperlayer.

[0086] Further, in order to obtain the semiconductor layers havingsubstantially the same crystalinity, the material of the double-layeredsemiconductor layer may be changed.

[0087] When a wavelength of the laser beam, which is hardly absorbed bythe semiconductor film having amorphous structure, is selected, it ispossible to adapt the state of crystal of two semiconductor layers to bethe same. For example, a continuous oscillation laser using the secondharmonic (532 nm) of an YV0 ₄ laser is selected, since the transmittancewith respect to the amorphous silicon film and the polysilicon film ishigh, it is possible to obtain the semiconductor layers havingsubstantially the same crystalinity each other. Further, since thedouble-layered semiconductor layers, which has irradiated with the laserbeam, become heat insulating layers each other, and since the period ofcooling time also becomes substantially the same, it is possible toobtain semiconductor layers that have substantially the same crystalstate. Further, since the double-layered semiconductor layers becomeheat insulating layers each other, and the period of cooling time iselongated, it is possible to generate a large size crystal. In thiscase, to the semiconductor layer of the lower layer, both of the heatradiating energy from the semiconductor layer of the upper layer and theenergy from the laser beam (laser beam, which has passed through theinsulating film and the semiconductor layer of the upper layer) aregiven; to the semiconductor layer of the upper layer, the energy fromthe laser beam and the energy of the laser beam, which has beenreflected by the semiconductor layer of the lower layer, are given.

[0088] Furthermore, in order to adapt so that the energy of the laserbeam, which is absorbed by the first semiconductor film having amorphousstructure, and the energy of the laser beam, which is absorbed by thesecond semiconductor film having amorphous structure, are the same, theenergy density given to the upper layer may be differed from the energydensity given to the lower layer. By focusing the laser beam so that theirradiation area of the upper layer is larger than the irradiation areaof the lower layer, the energy density may be adjusted by adjusting thefocus position or film thickness of the insulating film. When the laser,which passes through the upper layer, is a half; i.e., when thetransmittance is 50%, it is adjusted so that the area of the lower layerto be irradiated is a half of that of the upper layer.

[0089] Although an example, in which the semiconductor layer is adouble-layered structure, has been described above, by formingsemiconductor layers of triple layers or more on the different layerswith insulating films sandwiched therebetween, the integration may befurther increased. Further, when a plurality of TFTs of different kindsis formed on the same substrate, in an area, a double-layeredsemiconductor layer with insulating film sandwiched therebetween may beformed, and in another area, a single layered semiconductor layer may beformed and irradiated with laser beam. In particular, in a drivecircuit, a double-layered semiconductor layer is formed, and in thepixel section, a single layered semiconductor is formed and byirradiating with the above-described laser beam to form TFTsrespectively, a CMOS circuit, in which the occupied area is compacted byforming a double-layered semiconductor in the drive circuit, is formed,while, in the pixel section, a TFT having a single-layered semiconductoras the active layer is formed.

[0090] Although an example has been described here, in which thesemiconductor layer of the upper layer is irradiated directly with thelaser beam, the laser beam may be irradiate after the insulating filmhas been covered.

[0091] Conventionally, since it was difficult to irradiate a largeoutput laser stably, it was impossible to obtain such a constitution asthe invention. Although, it is possible to form the constitution as theinvention in a manner of solid-state growing, in the case ofdouble-layered semiconductor layer, since the crystallizing processesincrease simply twice and the time required for crystallizing processingbecomes enormously, it is not suitable for mass production. Even when itis try to obtain the constitution as the invention, since the number ofsteps is increased largely and the throughput is extremely decreased,the steps are not suitable for mass production.

[0092] According to the invention, although the number of steps isincreased in the patterning step of the first semiconductor layer andthe insulating film forming step for covering the first semiconductorlayer, the number of steps required for the crystallization is the same,without increasing the same, as the case that the number of thesemiconductor layer is one.

[0093] In the Japanese Patent Application Laid-Open No.2000-505241,discloses an art that, using a heat insulating layer as the lower layer,a semiconductor layer is formed being interposed with an insulating filmon the heat insulating layer, and a laser beam (wavelength 308 nm) isirradiated to obtain a large size crystal. However, according to thePublication, the laser is not a laser of large output; further there isno description that the heat insulating layer is used as the activelayer of the TFT. Accordingly, from the technique disclosed in theabove-described Publication, the invention is not conceivable. Accordingto the technique disclosed in the Publication, a laser beam ofwavelength range (308 nm), which does not pass through the amorphoussilicon, and the heat insulating layer of the lower layer is heated byonly the heat radiated from the semiconductor layer of the upper layer.Consequently, according to the technique disclosed in theabove-described Publication, the heat insulating layer of the lowerlayer is hardly crystallized.

[0094] Another constitution with respect to the manufacturing methodaccording to the invention is:

[0095] a manufacturing method of semiconductor device, which comprises:

[0096] a first step for forming a first semiconductor film havingamorphous structure on an insulated surface,

[0097] a second step for forming an first insulating film on thesemiconductor film,

[0098] a third step for forming a second semiconductor film havingamorphous structure on the first insulating film,

[0099] a fourth step for irradiating a laser beam to the secondsemiconductor film having amorphous structure by allowing the same topass through the first semiconductor film having amorphous structure andthe first insulating film to form the first semiconductor film havingcrystal structure and the second semiconductor film having crystalstructure simultaneously,

[0100] a fifth step for forming a second insulating film on the secondsemiconductor film having crystal structure,

[0101] a sixth step for forming a gate electrode on the secondinsulating film,

[0102] a seventh step for adding an impurity element for impartingN-type or P-type to the first semiconductor film having crystalstructure or the second semiconductor film having crystal structureusing the gate electrode as a mask.

[0103] Furthermore, another constitution with respect to themanufacturing method according to the invention is:

[0104] a manufacturing method of semiconductor device, which comprises:

[0105] a first step for forming a first gate electrode on an insulatedsurface,

[0106] a second step for forming a first insulating film for coveringthe first gate electrode,

[0107] a third step for forming a first semiconductor film havingamorphous structure on the first insulating film,

[0108] a fourth step for forming a second insulating film on thesemiconductor film,

[0109] a fifth step for forming a second semiconductor film havingamorphous structure on the second insulating film,

[0110] a sixth step for irradiating a laser beam to the secondsemiconductor film having amorphous structure by allowing the same topass through the first semiconductor film having amorphous structure andthe second insulating film to form the first semiconductor film havingcrystal structure and the second semiconductor film having crystalstructure simultaneously,

[0111] a seventh step for forming a third insulating film on the secondsemiconductor film having crystal structure,

[0112] an eighth step for forming a second gate electrode on the thirdinsulating film,

[0113] a ninth step for adding an impurity element for imparting N-typeor P-type to the first semiconductor film having crystal structure orthe second semiconductor film having crystal structure using the secondgate electrode as a mask.

[0114] Furthermore, in the above-described constitution, it ischaracterized in that the first gate electrode is the gate electrode ofthe TFT in which first semiconductor film having crystal structure isthe active layer, and the second gate electrode is the gate electrode ofthe TFT in which the second semi conductor film having crystal structureis the active layer.

[0115] The invention is applicable not only to the crystallization of asemiconductor film having amorphous structure but also to the annealingprocessing (typically, heat treatment such as activation processing orthe like), which uses the laser beam. Furthermore, still anotherconstitution with respect to the manufacturing method according to theinvention is a manufacturing method of semiconductor device, whichcomprises the steps of irradiating a laser beam to a first semiconductorfilm having amorphous structure or crystal structure disposed on aninsulated surface, an insulating film on the semiconductor film and asecond semiconductor film having amorphous structure or crystalstructure on the insulating film; and annealing the first semiconductorfilm and the second semiconductor film simultaneously.

[0116] To obtain the constitutions described in the above descriptionsof constitutions 1-6, the method thereof is not limited to theabove-described method in which two layers are crystallizedsimultaneously by means of a laser beam. It is possible to manufacturethe constitutions using a method other than the above-describedmanufacturing methods. However, if a method other than theabove-described manufacturing methods is used, the number of steps willbe increased and the period of processing time will be elongated. As forthe methods other than the above-described manufacturing methods, inwhich crystallizations are carried out simultaneously, for example,solid-phase growing method may be used; a method in which thecrystallization is carried out in a manner of heat treatment whileadding a metal element for accelerating the crystallization, may used;or the irradiation may be carried out simultaneously using light from alaser beam or a lamp light source. In the case that the crystallizationis carried out by irradiating laser beam from the front-face side andthe rear-face side, the wavelength range of the laser beam is notparticularly specified. Or, the crystallization may not be carried outsimultaneously, but one semiconductor layer may be crystallized first,and then, the other layer may be crystallized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0117]FIGS. 1A to 1D3 are illustrations showing Embodiment 1 (CMOScircuit);

[0118]FIGS. 2A to 2C are illustrations showing Embodiment 2 (OLED);

[0119]FIGS. 3A to 3B are illustrations showing Embodiment 2 (OLED);

[0120]FIGS. 4A to 4D3 are illustrations showing Embodiment 3 (LCD);

[0121]FIGS. 5A to 5C are illustrations showing Embodiment 3 (LCD);

[0122]FIGS. 6A to 6B are graphs showing relationships between wavelengthand transmittance and reflectance of amorphous silicon;

[0123]FIGS. 7A to 7B are graphs showing relationships between wavelengthand transmittance and reflectance of polysilicon.;

[0124]FIGS. 8A to 8B are block diagrams in a drive circuit (Embodiment1).;

[0125]FIGS. 9A to 9B are diagrams showing equivalent circuits(Embodiment 1).;

[0126]FIGS. 10A to 10B are a top view and a sectional view of an ELmodule;

[0127]FIG. 11 is a circuit diagram showing a constitution of a pixel(Embodiment 2);

[0128]FIGS. 12A to 12B are circuit diagrams showing constitution ofpixels (Embodiment 3);

[0129]FIGS. 13A to 13D3 are illustrations showing Embodiment 4;

[0130]FIGS. 14A to 14C are illustrations showing Embodiment 4;

[0131]FIGS. 15A to 15B are illustrations showing Embodiment 5;

[0132]FIGS. 16A to 16C are illustrations showing Embodiment 6;

[0133]FIGS. 17A to 17F are illustrations showing examples of electronicapparatus;

[0134]FIGS. 18A to 18D are illustrations showing examples of electronicapparatus; and

[0135]FIGS. 19A to 19C are illustrations showing examples of electronicapparatus.

PREFERRED EMBODIMENTS OF THE INVENTION

[0136] Hereinafter, Embodiments of the invention will be described.

[0137] Embodiment 1

[0138]FIG. 1 briefly show a typical semiconductor device to which theinvention is applied and a manufacturing method thereof. In this case, adescription will be made while taking an inverter circuit as an exampleof CMOS circuit.

[0139] In FIG. 1A, reference numeral 10 denotes a substrate havinginsulated surface; reference numeral 11 denotes a first electrode;reference numerals 12 a, 12 b denote first insulating films; referencenumeral 13 denotes a first semiconductor layer; reference numeral 14denotes a second insulating film; and reference numeral 15 denotes asecond semiconductor film.

[0140] In FIG. 1A, as for the substrate 10, a glass substrate, a quartzsubstrate, a ceramic substrate or a plastic substrate is applicable. Asfor the plastic substrate, since the heat resistance thereof is low, itis necessary to set the heat-treating temperature to a relatively lowlevel, for example, to a temperature lower than 300° C.

[0141] First of all, as shown in FIG. 1A, the first electrode 11 isformed on the substrate 10. The first electrode 11 is a portion, whichfinally becomes a gate electrode of a TFT at one side, and is able to beformed by carrying out patterning using a first mask after forming asingle layer or a laminated layer of a first conductive film. As for thematerial of the first conductive film, an element selected from Ta, W,Ti, Mo, Al and Cu, or an alloy material or a compound material comprisedof the foregoing elements as major components, is used. Also, as for theconductive film, a semiconductor film, which is typically exemplified bya polycrystalline silicon film doped with an impurity element such asphosphorous or the like, or an AgPdCu alloy may be used. Further,although it is not illustrated here, but before forming the firstelectrode 11, an insulating film comprised of silicon as the majorcomponent may be formed as a base film.

[0142] Next, the first insulating film 12 a, which covers the firstelectrode 11 and becomes the lower layer, is formed. Further, the firstinsulating film 12 b, which is flat and becomes the upper layer, isformed. In this case, although the first insulating film is exemplifiedas a double-layered structure, it may be formed into a single layeredstructure of an insulating film comprised of silicon as the majorcomponent, or into a structure laminated more than two layers. In thiscase, after forming the first silicon oxide film, which becomes thelower layer and laminating and forming the second silicon oxide film,which become the upper layer, by means of plasma CVD, a known flatteningprocessing; for example, a polishing processing, which is named asChemical-Mechanical Polishing (hereinafter, referred to as CMP) iscarried out. As another flattening processing, etch back method, inwhich, after forming a coating film (resist film or the like), etchingor the like is carried out to flatten the same, is also applicable. Asthe first insulating film 12 b, which becomes the upper layer, a flatsilicon oxide film may be formed by means of application. These firstinsulating films 12 a, 12 b finally become a gate insulating film of theTFT at one side. Total film thickness of the first insulating films 12a, 12 b is appropriately selectable within a range of 50 nm-200 nm.

[0143] Next, a first semiconductor film, which has a film thicknesswithin a range of 25-200 nm and an amorphous structure, is formed, andpatterning is carried out using a second mask to form the firstsemiconductor layer 13. Also, although the material of the firstsemiconductor film is not particularly limited to, but it is preferredthat, using silicon or silicon germanium (Si_(x)Ge_(1−x)(X=0.0001-0.02))alloy or the like, the first semiconductor film can be formed by a knownmeans (sputtering, LPCVD or plasma CVD or the like). Further,as forplasma enhanced CVD system, any of single wafer processing equipment andbatch processing system is applicable.

[0144] In this specification, a term “layer” means a state after aconfiguration has been formed by means of patterning or the like; and aterm “film” means a state after a film has been formed.

[0145] Next, the second insulating film 14, which covers the firstsemiconductor layer 13, is formed. The second insulating film 14 may beformed into a structure of a single layered film or being laminated morethan two layers of an insulating film comprised of silicon as the majorcomponent. The film thickness of the second insulating film 14 isappropriately selectable within the range of 10 nm-2 μm. However, whenthe finally manufactured two TFTS; i.e., CMOS circuits are driven, sincethe both exercise an influence on each other depending on the filmthickness and the material of the second insulating film 14, it ispreferred that the film thickness is more than the 200 nm.

[0146] Next, the second semiconductor film 15, which has a filmthickness within the range of 25-200 nm and an amorphous structure, isformed on the second insulating film 14. Also, although the material ofthe second semiconductor film is not particularly limited to, it ispreferred to form the second semiconductor film using silicon or silicongermanium (Si_(x)Ge_(1−x)(X=0.0001-0.02)) alloy or the like by means ofa known means (sputtering, LPCVD, plasma CVD or the like). Further, thesecond semiconductor film may be different from the first semiconductorfilm in the material or the film thickness.

[0147] Next, irradiation of laser beam is carried out to crystallizeboth of the above-described two layer semiconductors (FIG. 1A). In thiscase, since a laser beam that passes through the second semiconductorfilm 15 is irradiated to the first semiconductor layer 13, when thelaser beam has at least wavelength and energy capable of passing throughthe second semiconductor film and crystallizing the two layersemiconductors, the laser beam is not particularly limited to. Whencrystallizing semiconductor films having amorphous structure, to obtaina large size crystal, it is preferred to use a solid-state laser capableof continuous oscillation, and to apply the second harmonic-fourthharmonic of the basic wave. The second harmonic (532 nm) and the thirdharmonic (355 nm) of the Nd: YVO₄ laser (basic wave 1064 nm) is appliedto. A laser beam radiated from the YVO₄ laser of continuous oscillationof 10 W output is converted by a nonlinear optical element to obtainthese harmonics. Also, a method, in which an YVO₄ crystal and anonlinear optical element are set in a resonator and a harmonic isirradiated, is available. Preferably, the laser beam is reformed into ashape of rectangular or elliptical at the irradiated surface by theoptical system and is irradiated onto the object to be processed. Energydensity at this time is required to be 0.01-100 MW/cm² or so(preferably, 0.1-10 MW/cm²). And the semiconductor film is irradiatedwhile being made a relative movement with respect to the laser beam at aspeed of 0.5-2000 cm/s or so. It is preferred to irradiate the beam atan angle with respect to the surface of the semiconductor film so as notallow the incident light and the reflected light at the rear face of thesubstrate to interfere each other. In this case, since the reflectancechanges remarkably with respect to the changes of the incident angle ofthe laser beam, it is preferred to adopt the angle of the laser beam sothat the changes of the reflectance is within 5%.

[0148] Also, when a laser of continuous oscillation is used, it ispreferred to scan the area to irradiated by the laser beam while movingthe same in the direction of the channel length (in the direction ofmovement of the carrier) of the TFT, which is finally formed.

[0149] Further, the energy owing to the irradiation of theabove-described laser beam, which has been absorbed in the secondsemiconductor film, changes into heat and is transmitted to the firstsemiconductor layer. Accordingly, total energy absorbed by therespective semiconductor layers is made to be even, and the coolingperiod between the layers becomes substantially the same. Owing to beingmade to be even, since the heat of the melted silicon is maintained eachother resulting in an elongated cooling period, it is possible to allowa large size crystal to be generated. That is to say, it is possible toobtain a semiconductor film that has the crystalinity better than thecase that a single-layered amorphous silicon film is crystallized bymeans of a laser beam of continuous oscillation. Furthermore, as for thetotal energy being made to be even, a better effect is obtained when thefilm thickness of the second insulating film, which is sandwichedbetween the layers, is thinner. In order to obtain the effect, accordingto the invention, two semiconductor layers are disposed with only thesecond insulating film being sandwiched between them.

[0150] Furthermore, owing to the above-described irradiation of thelaser beam, the laser beam reflected to the first semiconductor layer isirradiated again to the second semiconductor film and absorbed thereby.And the reflection is repeated between the first semiconductor layer andthe second semiconductor film and absorbed by the respectivesemiconductors. Also, in the case that a conductive layer havingreflectivity is provided below the first semiconductor layer, it ispossible that the laser beam due to the reflection from the conductivelayer is absorbed. Further, it is also possible that the laser beam dueto the reflection from the substrate and the stage is absorbed.

[0151] Still further, although the laser beam may be focused to eitherof the semiconductors, when the beam is focused to the firstsemiconductor layer of the lower layer, although it depends on the filmthickness of the second insulating film, the energy density irradiatedto the first semiconductor layer can be adapted to be larger than theenergy density irradiated to the second semiconductor film. Further, thefilm thickness of the first semiconductor layer and the film thicknessof the second semiconductor film may be adjusted in accordance with thetransmittance of the laser beam with respect to the second semiconductorfilm so that the absorbed amounts of the total energy are the same.

[0152] Still furthermore, the above-described laser beam may beirradiated after adding a metal element exemplified by nickel, whichaccelerates the crystallization of the silicon, to the secondsemiconductor film having amorphous structure. Since the conditionalmargin for the laser beam is widened by adding the nickel, it becomeseasy to form semiconductor film having a preferable crystal structure.Also, when the crystallization is carried out using a metal element, itis preferred to carry out gettering to remove the added metal element inthe following step from the semiconductor film.

[0153] Thus, after forming the first semiconductor layer 16 havingcrystal structure and the second semiconductor film having crystalstructure, pattering is carried out using a third mask to form a secondsemiconductor layer 17. In this case, in order to establish the contactwith wiring later, the size of the first semiconductor layer 16 is madedifferent from that of the second semiconductor layer 17. However, it isnot limited to the configuration of the respective semiconductor layershere, but at least it is required that the finally formed channelforming areas overlap with each other with the second insulating film 14being sandwiched between them. Further, in this case, although thepatterning is carried out after carrying out the crystallization bymeans of the laser beam, the patterning may be carried out beforecarrying out the crystallization by means of the laser beam.

[0154] When it is necessary to control the threshold, channel doping forcontrolling the threshold may be carried out after the firstsemiconductor layer 16 having crystal structure and the secondsemiconductor film having crystal structure have been formed.

[0155] Next, a third insulating film 18, which covers the secondsemiconductor layer 17, is formed. The third insulating film 18 may beformed into single layered structure or a structure being laminated morethan two layers of an insulating film comprised of silicon as the majorcomponent. Also, the third insulating film comprised of oxidized filmmay be formed only on the second semiconductor layer by means of thermaloxidation. The third insulating film 18 becomes finally another gateinsulating film. The film thickness of the third insulating film 18 ispreferably selectable within the range of 50 nm-200 nm. In this case,although the third insulating film 18 is formed after carrying out thecrystallization, the crystallization may be carried out by irradiatingthe above-described laser beam allowing passing through the thirdinsulating film after the third insulating film has been formed.

[0156] Next, a contact hole, which reaches the first electrode 11, isformed using a fourth mask. Then, after forming the second conductivefilm, a second electrode 19, which is electrically connected with thefirst electrode 11, is formed using a fifth mask (FIG. 1B). The secondconductive film is formed with a material that is an element selectedfrom Ta, W, Ti, Mo, Al and Cu, or, an alloy material or a compoundmaterial comprised of the above-described element as the majorcomponent. As for the conductive film, a semiconductor film exemplifiedby polycrystalline silicon film, which is doped with an impurity elementsuch as phosphorous or the like, or an AgPdCu alloy may be used. Thesecond electrode 19 finally becomes another gate electrode.

[0157] Next, an impurity element, which imparts the semiconductor N-typeor P-type, is added using the second electrode 19 as a mask (FIG. 1C).In this case, N-type impurity areas 20, 21 are formed in a manner ofself-aligning by adding phosphorous to the first semiconductor layer 16and allowing the same to pass through the third insulating film 18, thesecond semiconductor layer 17 and the second insulating film 14 by meansof ion doping. Then, P-type impurity areas 22, 23 are formed in a mannerof self-aligning by adding boron to the second semiconductor layer 17 bymeans of ion doping and allowing the same to pass the third insulatingfilm 18. By appropriately setting the doping conditions respectively inaccordance with the depth from the surface, it is possible to add adesired impurity density respectively to the first semiconductor layerand the second semiconductor layer disposed in the different depthrespectively. Since the boron is small in atom size and is hard toactivate after the addition, the second semiconductor layer is made tobe amorphous by giving doping damage by means of doping of phosphorous.The order of the above-described doping is not particularly limited to.Also, in place of the ion doping, ion implantation after mass separationmay be applied to. As for the doping, since the added amount of thedopant varies depending on the depth direction, in the area where actualdepth from the surface differs due to the second semiconductor layer,which lies above the same; i. e., in the area adjacent to the channelforming area 28 in the impurity areas 20, 21, the dopant is added at alow density to form an LDD area (not shown in the Figures).

[0158] Further, after carrying out the first doping on the secondsemiconductor layer, the third insulating film 18 may be removedselectively excluding only the portion where overlaps with the secondelectrode 19 by means of dry etching to expose the second semiconductorlayer, and the addition to the first semiconductor layer may be carriedout by carrying out the second doping. Further, in the case that theselective ratio between the second semiconductor layer and the secondinsulating film is high after the doping has been carried out, the firstsemiconductor layer may be exposed by means of dry etching excludingonly the portion where overlaps with the second semiconductor layer inthe second insulating film. When the first semiconductor layer and thesecond semiconductor layer have been exposed, it makes the followingstep to form a contact hole, which reaches the first semiconductorlayer, easy.

[0159] Next, in order to activate the added impurity element, heattreatment and strong light irradiation from a lamp light source or laserbeam irradiation are carried out. Also, two layers may be activatedsimultaneously using a laser beam, which passes through the secondsemiconductor layer. When second harmonic-fourth harmonic are used forthe activation using a solid-state laser (YAG laser, YVO₄ laser, YLFlaser, or full-solid infrared laser of semiconductor laser excitation,or the like), which is capable of continuous oscillation, approximately0.01-100 MW/cm² (preferably, 0.01-10 MW/cm²) is required. Further, theirradiation is carried out at a speed of approximately 0.5-2000 cm/swhile shifting the semiconductor film with respect to the laser beam.Furthermore, the irradiation may be carried out by means of a stronglight or laser beam from the both sides; i.e., from the rear-face sideand the front-face side thereof. When the activation is made byirradiating the laser beam from the front-face side and the rear-faceside, the wavelength range of the laser beam is not particularly limitedto. Along with the activation, the plasma damage to the insulating film,which becomes the gate insulating film and the plasma damage to theboundary between the insulating film and the semiconductor layer, whichbecomes gate-insulating film, can be restored.

[0160] Next, an interlayer insulating film 24 is formed and is subjectedto hydride treatment. And then, contact holes, which reach the impurityareas 20-23, are formed using a sixth mask. When the enough selectiveratio is provided, each contact hole may be formed simultaneously; maybe formed separately; or may be formed step-by-step. The contact holes,which reach the impurity areas 22, 23 of the second semiconductor layer17, are formed in the area inner than the area where the contact holes,which reach the impurity areas 20, 21 of the first semiconductor layer16. Then, a third conductive film is formed, and then wirings 25-27,which electrically connect to the respective impurity areas 20-23, areformed using a seventh mask (FIG. 1D1).

[0161] By performing the above-described processes, a P-channel type TFT30 of top gate structure, which has the second electrode 19 as the gateelectrode, the third insulating film 18 as the gate insulating film, andthe source area 23, the drain area 22 and a channel forming area 29sandwiched between these areas as the active layer, the source wiring 27for connecting to the source area 23, and the drain wiring 25 forconnecting to the drain area 23 (22), is completed. Additionally, anN-channel type TFT of inversed stagger structure, which has the firstelectrode 11 as the gate electrode, the source area 21, the drain area20 and the channel forming area 28 sandwiched between these areas as theactive layer, is completed.

[0162] Also, if necessary, a passivation film (protection film)comprised of nitride film may be formed by covering the TFTappropriately.

[0163] Further, in the manufacturing process according to the invention,CMOS circuit can be manufactured using seven masks. Conventionally, whenmanufacturing CMOS circuits aligned in parallel to each other, six masksare required; i.e., a mask for patterning semiconductor layer, a maskfor patterning gate electrode, a doping mask of impurity element forimparting N-type, a doping mask of impurity element for impartingP-type, a mask for patterning contact holes and a mask for patterningwirings. According to the invention, by adding only one mask, requiredarea of the CMOS circuit can be reduced largely.

[0164]FIG. 1D2 shows an example of the top view. A sectional view, whichis taken along the chain line A-A′ in FIG. 1D2, correspond to FIG. 1D1.In the top view, although the island-like second electrode 19 isconnected to the first electrode 11, which is branched from a wiring,the invention is not limited to the top view. For example, the firstelectrode may be formed island-like and the second electrode may beconnected to a wiring. Also, it is illustrated that the width of thefirst electrode 11 is the same as that of the second electrode 19.However, depending on the patterning accuracy, the actual width of thefirst electrode 11 differs from the width of the second electrode 19.For example, when the width of the first electrode is formed larger thanthat of the second electrode, it is structured so that apart of thefirst electrode 11, which is the gate electrode and the impurity areas20, 21, which are the source area or drain area, are overlapped witheach other sandwiching the first insulating films 12 a, 12 b. Also, whenthe width of the first electrode is formed smaller than that of thesecond electrode, an offset area (comprised of the same material as thechannel forming area) is formed between the channel forming area and thesource area (or drain area).

[0165] As shown in FIG. 1D2, the second electrode 19 is connected to thefirst electrode 11. The first electrode 11 is the gate electrode of theN-channel type TFT that comprises the source area 21, the drain area 20and the channel forming area 28 sandwiched between these areas as theactive layer. Further, although the size of the first semiconductorlayer and that of the second semiconductor layer differ from each otherin order to establish the contact therebetween, the configuration is notparticularly limited thereto. Furthermore, the channel forming area 28of the N-channel type TFT is the same as the channel length L of thechannel forming area 29 in the P-channel type TFT. On the other hand, inthis case, in order to illustrate the positional relationship so as tobe understandable, although it is shown that the N-channel type TFT isslightly larger in the channel width W, the same may be the same as thatof the P-channel type TFT. The N-channel type TFT is the inversedstagger type TFT and the gate insulating film is the first insulatingfilms 12 a, 12 b. Since the drain area 20 is electrically connected tothe drain wiring 25, it is possible to form CMOS circuit by combiningcomplementally with the above-described P-channel type TFT 30. FIG. 1D3shows an example of an equivalent circuit diagram in a CMOS circuit.

[0166] In the case that the CMOS circuit is driven, a random minusvoltage (a minus voltage larger than the threshold of the P-channel typeTFT 30) is applied to the gate wiring (including first electrode 11 andthe second electrode 19), since the P-channel type TFT 30 becomesON-state and the N-channel type TFT becomes OFF-state, the voltage Vccof the power supply voltage line, which is connected to the sourcewiring 27, is given to the drain wiring 25. On the other hand, when arandom plus voltage (a plus voltage larger than the threshold of theN-channel type TFT) is applied to the gate wiring, since the N-channeltype TFT becomes ON-state and the P-channel type TFT 30 becomesOFF-state, an electric potential same as the GND, which is connected tothe source wiring, (or fixed potential) is given to the drain wiring 25.

[0167] A simulation was carried out using the same structure as thatshown in FIG. 1. The conditions of the simulation are as describedbelow: the film thickness in the first insulating films 12 a, 12 b andthe third insulating film 18 is 110 nm; the channel size (L/W) is 7 μm/8μm; the film thickness in the first semiconductor layer 16 and thesecond semiconductor layer 17 is 50 nm; the carrier (B: boron) densityin the source area or the drain area of the P-channel type TFT 30 is1×10²⁰ atoms/cm³ and the carrier (B: boron) density in the channelforming area 29 is 2×10¹⁶ atoms/cm³; the carrier (P: boron) density inthe source area or drain area of the N-channel type TFT is 1×10²⁰atoms/cm³ and the carrier(B: boron)density in the channel forming area28 is 2×10 ¹⁶ atoms/cm³. Further, it is assumed that the film quality ofthe first semiconductor layer 16 and that of the second semiconductorlayer 17 are the same.

[0168] When a voltage of −10V was applied to the second electrode 19that was the gate electrode (in the case that the N-channel type TFT wasin the OFF-state), without depending on the film thickness (50 nm-200nm) of the second insulating film 14, the Vth (threshold) of theP-channel type TFT 30 showed little changes and fell within the range of−2.44V-−2.47V. As for the S-value (sud-threshold coefficient), when thefilm thickness of the second insulating film 14 was 50 nm, the value was0.34 V/dec; when the same was 100 nm, the value was 0.30 V/dec; and thesame was 200 nm, the value was 0.27 V/dec. Since the larger filmthickness of the second insulating film 14 resulted in the better value,it is preferred that the film thickness of the second insulating film 14is 200 nm or more.

[0169] Also, when a voltage of 10V was applied to the second electrode19 that was the gate electrode (when the P-channel type TFT is in theOFF-state), without depending on the film thickness (50 nm-200 nm) ofthe second insulating film 14, the Vth (threshold) of the N-channel typeTFT 30 showed little changes and fell within the range of 1.58V-1.66V.As for the S-value, when the film thickness of the second insulatingfilm 14 was 50 nm, the value was 0.32 V/dec; when the same was 100 nm,the value was 0.30 V/dec; and when the same was 200 nm, the value was0.28 V/dec. Since the larger film thickness of the second insulatingfilm 14 resulted in the better value, it is preferred that the filmthickness of the second insulating film 14 is 200 nm or more.

[0170] With the purpose of comparison, it is assumed that the respectivecharacteristic values of a generally structured P-channel type TFT, inwhich the gate insulating film is 110 nm; the semiconductor layer is 50nm; the carrier (B: boron) density in the source area or drain area is1×10²⁰ atoms/cm³, and the carrier (B: boron) density in the channelforming area is 2×10¹⁶ atoms/cm³, are: threshold =−2.09V; the S-value is0.25 V/dec. Also, the respective characteristic values of the generallystructured N-channel type TFT, in which the carrier(P: phosphorous)density in the source area or drain area is 1×10²⁰ atoms/cm³, and thecarrier (B: boron) density in the channel forming area is 2×10¹⁶atoms/cm³, are: threshold=1.31V; S-value is 0.26 V/dec.

[0171] Furthermore, in the ON-current value and the OFF-current value,since there are little differences, it is possible to drive the circuitas the CMOS circuit with no problem. However, in the above-describedsimulation, it is assumed that the semiconductor layer of the generallystructured TFT and the semiconductor layer of the TFT according to theinvention have the same film quality. According to the invention, in thecase that the laser beam is irradiated to fuse the double-layeredsemiconductor layers, since the absorbed heat is maintained each otherand the period of cooling time of the fused silicon become longer thanthe case that a single-layered semiconductor layer is fused, it ispossible to obtain a semiconductor film that has an preferablecrystalinity.

[0172] According to Embodiment 1, an example, in which an impurityelement for imparting N-type is add to the first semiconductor layer 16,and an impurity element for imparting P-type is added to the secondsemiconductor layer 17, is given. However, the impurity element forimparting P-type may be added to the first semiconductor layer 16, andthe impurity element for imparting N-type may be added to the secondsemiconductor layer 17.

[0173] Further, according to Embodiment 1, an example, in which, after afilm having amorphous structure has been formed as the firstsemiconductor layer, the second insulating film has been formed, andthen the second semiconductor film having amorphous structure has beenformed, semiconductor layer having double-layered crystal structure isobtained by crystallizing by means of the above-described laser beam, isgiven. However, the semiconductor layer having the double-layeredcrystal structure may be obtained in such manner that, after forming thefirst semiconductor layer by forming a film having crystal structure bymeans of LPCVD or the like, carrying out patterning, forming the secondinsulating film, and them forming the second semiconductor film havingamorphous structure, the second semiconductor film is crystallized bymeans of the above-described laser beam and at the same time the firstsemiconductor layer is annealed.

[0174] Further, the invention is not limited to the TFT structure shownin FIG. 1D1. If necessary, it may be such structured that a low densitydrain (LDD: Lightly Doped Drain) having LDD area between the channelforming area and the drain area (or source area) is formed using a mask.In this structure, an area where is added with impurity element at a lowdensity is disposed between the channel forming area and the source areaor drain area formed by adding an impurity element at a high density,and this area is defined as LDD area.

[0175] Further, the TFT shown in FIG. 1D1 is a single gate structure.However, it is not limited thereto, but a double gate structure, whichhas two channel forming areas, may be, formed by disposing two gateelectrodes flatly in parallel, or a multi-gate structure, which has aplurality more than three of channel forming areas, may be formed.

[0176] According to the invention, it is possible to largely reduce thearea occupied by the CMOS circuit. Accordingly, it is made possible tominiaturize the drive circuit including the CMOS circuit.

[0177] Embodiment 2

[0178] Hereinafter, referring to FIG. 2 and FIG. 3, a light-emittingdevice having a typical OLED, in which the invention is applied to, willbe described. In this case, a light-emitting device, in which one pixelhas two TFTs (first TFT 55, second TFT 56), will be described as anexample.

[0179] In the sectional view shown in FIG. 2A, reference numeral 40denotes a substrate; 41 denotes a first electrode (gate wiring); 42denotes a first insulating film, 43 a and 43 b denote a source area ordrain area, respectively; 43C denotes a channel forming area; 44 denotesa second insulating film; 45 a denotes a source area; 45 b denotes adrain area; 45 c denotes a channel forming area; 46 denotes a thirdinsulating film; 47 denotes a second electrode; 48 a and 48 b denote afourth insulating film respectively; 49 denotes a cathode or anode; 50denotes a source wiring; 51 denotes a connection electrode, 52 denotes apower supply wiring; 53 denotes a connecting electrode; and 54 denotes abank.

[0180] As for the substrate 40, a glass substrate, a quartz substrate, aceramic substrate, a plastic substrate or the like is applicable to.Also, the first electrode 41, the second electrode 47, the source wiring50, the connecting electrodes 51, 53, and the power supply wiring 52 areformed into a single layer of an element selected from Ta, W, Ti, Mo, Aland Cu; or, of an alloy material or compound material comprised of theabove-described elements as the major components; or, into alaminated-layer thereof. Further, these electrode and wiring, asemiconductor film exemplified by a polycrystalline silicon film dopedwith impurity element of phosphorous or the like, or an AgPdCu alloy maybe applied to. Furthermore, as for the first insulating film 42, thesecond insulating film 44, the third insulating film 46, the fourthinsulating films 48 a, 48 b, and the bank 54, may be formed with asingle layered or double or more layered film of a insulating film(silicon oxide film, silicon nitride film, silicon nitride/oxide film orthe like), which is comprised of silicon as the major component, or anorganic resin film by means of application, plasma CVD, sputtering,LPCVD or the like. Still further, semiconductor layers including 43 a-43c and 45 a-45 c may be formed into a film respectively using silicon orsilicon germanium (Si_(x)Ge_(1−x)(X=0.0001-0.02)) alloy or the like byknown means (sputtering, LPCVD, plasma CVD or the like) and crystallizethe same.

[0181]FIG. 2B shows a top view. The sectional view taken along the chainline in FIG. 2B corresponds to FIG. 2A.

[0182] Since FIG. 2A and FIG. 2B are illustrations showing the stagethat the cathode or anode of the OLED has been formed, either theorganic light-emitting layer or the anode or cathode formed thereon isnot shown. Further, in FIG. 2, although holding capacity is not shown,the holding capacity may be provided or may not be provided inaccordance with the driving method of the OLED.

[0183] To control the current, which flows to the OLED, by means of aTFT, the methods therefor are roughly categorized into two groups. Inparticular, a method, in which the current is controlled within thevoltage range named as saturated area, and a method, in which thecurrent is controlled within the voltage range up to the saturated area,are available. In this specification, the range of Vd, in which thecurrent value becomes substantially constant, in the Vd-Id curve, isdefined as saturated area. The invention is not limited to the drivingmethod of the OLED, but any driving method may be applied to.

[0184] Since the manufacturing method of the device is substantially thesame as the steps described in Embodiment 1, the description thereofwill be given just simply, and the points different therefrom will bedescribed below.

[0185] First of all, a base insulating film (not shown in the drawings)is disposed on the substrate 40 having an insulated surface, and thefirst electrode 41, which will become the gate electrode of a first TFT,is formed. Then, the first insulating film 42 (film thickness within arange of 50 nm-200 nm), which will become the gate insulating film ofthe first TFT, and a first semiconductor film (film thickness within arange of 25-200 nm) having amorphous structure are formed. Here, inorder to prevent the boundary from being contaminated, the firstinsulating film 42 and the first semiconductor film are formedsuccessively by means of plasma CVD without allowing the same to contactwith the air.

[0186] Next, The first semiconductor film is formed into a desiredconfiguration by means of patterning. Then, the second insulating film44 and a second semiconductor film (film thickness within a range of25-200 nm) having amorphous structure are formed. Here, in order toprevent the boundary from being contaminated, the second insulating film44 and second semiconductor film are formed successively by means ofplasma CVD without allowing the same to contact with that air. The filmthickness of the second insulating film 44 may be selected appropriatelyfrom a range of 10 nm-2μm.

[0187] Next, the first semiconductor layer having amorphous structureand the second semiconductor film having amorphous structure arecrystallized. Although the crystallizing method is not particularlylimited to, in this case, a second harmonic (532 nm) or a third harmonic(355 nm), which is output from an YVO₄ laser of 10 W continuousoscillation output, is applied to. Preferably, the laser beam isreformed into an elliptical form at the irradiated surface by means ofan optical system, and the first semiconductor layer having amorphousstructure and the second semiconductor film having amorphous structureare irradiated. The energy density at this time is required to beapproximately 0.01-100 MW/cm² (preferably 0.1-10 MW/cm²). Thesemiconductor film is irradiated while being shifted at a speed ofapproximately 0.5-2000 cm/s with respect to the laser beam relatively.By irradiating the laser beam to the first semiconductor layer havingamorphous structure and the second semiconductor film having amorphousstructure, since the absorbed heat is maintained respectively and theperiod of cooling time is elongated, it is possible to allow growinginto a large diameter crystal. That is to say, it is possible to obtainsemiconductor film, which has the crystalinity better than the case thatthe amorphous silicon film of single layer is crystallized by means ofthe continuous oscillation laser beam.

[0188] Next, after carrying out the patterning of the above-describedsecond semiconductor film, the surface of the second semiconductor layeris rinsed to form the third insulating film 46, which is comprised of asingle layer or laminated-layer of insulating film of silicon as themajor component. Also, a third insulating film of oxidized film may beformed only on the surface of the second semiconductor layer by means ofthermal oxidization. The third insulating film 46 will finally becomethe gate insulating film of the second TFT. The film thickness of thethird insulating film 46 is selectable from a range of 50 nm-200 nm.

[0189] Next, the second electrode 47 is formed on the third insulatingfilm. The second electrode 47 will finally become the gate electrode ofthe second TFT. In this case, although the width second electrode 47 isset to be narrower than the width of the first electrode 41 in thechannel length direction, it is not limited thereto. Also, when thewidth of the first electrode is set to be narrower than that of thesecond electrode, an offset area (comprised of the same material as thatof the channel forming area) is formed between the channel forming areaand the source area (or drain area).

[0190] Next, by carrying out the ion doping or ion implantation usingthe second electrode 47 as the mask, an impurity element for impartingN-type or P-type to the two semiconductor layers is added in a manner ofself-aligning to form the impurity areas 43 a, 43 b, 45 a and 45 b.Since the second electrode 47 is used as the mask, the channel length Lbetween the first TFT of the channel forming area 43 c and the secondTFT of the channel forming area 45 c becomes equal to each other. In thefirst TFT, the first electrode 41, which is the gate electrode, and theimpurity areas 43 a, 43 b, which are the source area or drain area, arepartially overlapped with each other with the first insulating film 42,which will become the gate insulating film, sandwiched therebetween.Since, in the doping, since the dopant amount to be added variesdepending on the depth direction, in the area where the depth from thesurface varies due to the second semiconductor layer above the same,i.e., the area adjacent to the channel forming area 43 c in the impurityareas 43 a, 43 b, actually, the dopant is added at a low density, andLDD area (not shown in the Figures) is formed.

[0191] By adding N-type impurity element to the first semiconductorlayer, it is possible to make the first TFT into the N-channel type TFT;while by adding P-type impurity element to the first semiconductorlayer, it is possible to make the first TFT into the P-channel type TFT.Also, By adding N-type impurity element to the second semiconductorlayer, it is possible to make the second TFT into the N-channel typeTFT; while by adding P-type impurity element to the second semiconductorlayer, it is possible to make the second TFT into the P-channel typeTFT.

[0192] The practitioner of the invention can appropriately selectwhether the second TFT is to be the N-channel type TFT or the P-channeltype TFT.

[0193] Next, in order to activate the added impurity element, heattreatment and strong light irradiation from a lamp light source or laserbeam irradiation are carried out. Also, two layers may be activatedsimultaneously using a laser beam, which passes through the secondsemiconductor layer. When second harmonic-fourth harmonic are used forthe activation using a solid-state laser (YAG laser, YVO₄ laser, YLFlaser, or full-solid infrared laser of semiconductor laser excitation,or the like), which is capable of continuous oscillation, approximately0.01-100 MW/cm² (preferably, 0.01-10 MW/cm²) is required. Further, theirradiation is carried out at a speed of approximately 0.5-2000 cm/swhile shifting the semiconductor film relatively with respect to thelaser beam. Furthermore, the irradiation may be carried out by means ofa strong light or laser beam from the both sides; i.e., from therear-face side and the front-face side thereof. When irradiating thelaser beam from the front-face side and the rear-face side makes theactivation, the wavelength range of the laser beam is not particularlylimited to. Along with the activation, the plasma damage to theinsulating film, which becomes the gate insulating film and the plasmadamage to the boundary between the insulating film and the semiconductorlayer, which becomes gate-insulating film, can be restored.

[0194] Next, the lower layer 48 a is formed as a planarizing filmcomprised of an organic resin, and the upper layer 48 b is formed as aninterlayer insulating film comprised of an inorganic insulating film.After carrying out a hydride treatment, the cathode or anode 49 isformed. It is selectable for a practitioner of the invention toappropriately decide whether the item 49 is to be a cathode or an anode.Although, not shown in the Figures, in the I/O terminal section, padelectrode may be formed simultaneously.

[0195] Next, using a mask, contact holes, which reach to impurity areas43 a, 43 b, 45 a and 45 b respectively, are formed. Also, although notshown in the figures, in the I/O terminal section, a contact hole, whichreaches to the first electrode 41, is formed. The contact holes, whichreach to the impurity areas 45 a, 45 b in the second semiconductorlayer, is formed inner side than the contact holes, which reach theimpurity areas 43 a, 43 b in the first semiconductor layer. Next, athird conductive film is formed, and using a mask, wirings andelectrodes 50-53, which connect electrically with the respectiveimpurity areas, are formed. Also, the connecting electrode 53 connectselectrically to the cathode or anode 49. Further, although not shown inthe figures, in the I/O terminal section, an electrode, which connectsthe first electrode 41 and the pad electrode, is formed. Next, in orderto cover the end portion of the cathode or anode 49, at the both endsthereof, an insulator 54 named as bank is formed.

[0196]FIG. 2A shows a sectional view at a point when the above-describedsteps have been completed; FIG. 2B is a top view thereof.

[0197] Although an example, in which two TFTs are provided to one pixel,is given here, it is needless to say that the same is not limited tothat.

[0198] Further, if necessary, a passivation film (protection film)comprised of nitride film, which covers the TFTs, may be formedappropriately.

[0199] Next, on the cathode or anode 49 of which both ends are coveredwith bank 54, an EL layer (organic compound material layer) and an anodeor cathode of the OLED is formed. In the case that the item 49 is thecathode, an anode is provided to the EL layer; while in the case thatthe item 49 is the anode, a cathode is provided to the EL layer.Further, although not shown in the figures, in the I/O terminal section,the cathode or anode may be functioned as the wiring common to everypixel, and a terminal electrode via the connecting wiring may be formed.

[0200] As for the EL layer, by appropriately combining with alight-emitting layer, a charge carrier layer or a charge injectionlayer, an EL layer (a layer for emitting light and for allowing thecarrier to move) is formed. For example, an organic EL material from lowmolecular group or an organic EL material from high molecular group maybe used. As for the EL layer, a thin film comprised of light-emittingmaterial (singlet compound), which emits light (fluorescence) viasinglet excitation, or a thin film comprised of light-emitting material(triplet compound), which emits light (phosphorescence) via tripletexcitation may be used. Further, as for the charge carrier layer and thecharge injection layer, an inorganic material such as silicon carbide orthe like may be used. As for these organic EL material and inorganicmaterial, a known material may be used. The EL layer is formed as a thinfilm layer of approximately 100 nm in thickness. Accordingly, it isnecessary to increase the flatness of the surface of the item 49, whichis formed as a cathode or anode.

[0201] Further, as for the material used for the cathode, it ispreferred to use a metal having a small work function (typically, ametal element included in periodic function 1-familly or 2-familly) oran alloy that includes such a material. Since the smaller work functionincreases the light-emitting efficiency, as for the material used forthe cathode, an alloy material including Li (lithium), which is one ofthe alkali metals, is preferred.

[0202] As for the conductive film used for the anode, a material, whichhas the work function larger than that of the material for forming thecathode, is used. One of the following materials such as an ITO(indiumtin oxide alloy ), an indium zinc oxide alloy (In₂O₃—ZnO), a zinc oxide(ZnO)or the like; and further, a material of which sheet resistance islower than that of the ITO; in particular, a material such as platinum(Pt), chrome (Cr), Tungsten (W) or nickel (Ni) may be used.

[0203] By carrying out the above-described steps, a second TFT 56 of topgate type, which is connected with the OLED, and the first TFT 55 ofinversed stagger type, in which the gate electrode 47 of second TFT isconnected to the source area or drain area, are formed.

[0204] The top gate type second TFT 56 includes a second electrode 47 asthe gate electrode, a third insulating film 46 as the gate insulatingfilm, an impurity area 45 a, 45 b and a channel forming area 45 csandwiched between two impurity areas as the active layers, theconnecting electrode 53 that connects with the impurity area 45 a andthe power supply wiring 52 that connects with the impurity area 45 b.

[0205] Also, the inversed stagger type first TFT 55 includes a firstelectrode 41 as the gate electrode, the first insulating film 42 as thegate insulating film, the impurity areas 43 a, 43 b and the channelforming area 43 c sandwiched between two impurity areas as the activelayers, the connecting electrode 51 that connects with the impurity area43 b and the source wiring 50 that connects with the source wiring 50.

[0206] Next, it is preferred that any substance such as moisture, oxygenor the like, which accelerates the deterioration of the EL layer due tothe oxidation, is prevented from coming therein from the external, bysealing the OLED, which has at least the cathode, the organic compoundlayer and the anode, by means of a protection film, a sealing substrate,a silicon oil or sealing can. However, as for the I/O terminal section,which is required to be connected with the FPC, it is not necessary toprovide with a protection film or the like.

[0207]FIG. 2C shows an equivalent circuit diagram. The equivalentcircuit diagram shown in FIG. 2C is the case that two TFTs are separatedby the second insulating film so as not to give any influence on eachother. In FIG. 2C, reference numeral 57 denotes a light-emittingelement, and 58 denotes a power supply wiring.

[0208] When the second TFT 56 that supplies a current to the OLED isformed as a P-channel type TFT, a connection shown in FIG. 3A is made.Also, when the second TFT 56 that supplies a current to the OLED isformed as an N-channel type TFT, a connection shown in FIG. 3B is made.In FIG. 3A and FIG. 3B, although only the TFT that supplies a current tothe OLED is shown, to end of the gate electrode of the TFT, variouscircuits comprised of a plurality of TFTs or the like may be provided.It is needless to say that the same is not particularly specified.

[0209] When a CMOS circuit described in the Embodiment 1 is adopted,since the gate electrode is common, the upper and lower gate voltagesare the same. However, in the Embodiment 2, the gate electrode is notcommon. In the Embodiment 2, since the voltage applied to the gateelectrode 41 of the lower side is different from the voltage applied tothe gate electrode 47 of the upper side, the same are driven while beingscanned. That is to say, it is possible to apply a voltage from the gateelectrode 41 to the second TFT 56; it is possible to apply a voltagefrom the gate electrode 47 to the first TFT 55. Owing to thisarrangement, it is possible to obtain an effect similar to the effect ofdual gate structure, in which channels (dual channel) are formed aboveand under one semiconductor layer; i.e., it is possible to reduce thedispersion in the threshold, and further, it is possible to reduce theOFF-current.

[0210] Under such conditions that the second TFT is the P-channel typeTFT, and the first TFT is the N-channel type TFT, the gate electrode ofthe second TFT is in the ON-state; i.e., the same is applied with avoltage of −10V, and the gate electrode of the first TFT is in theON-state; i.e., the same is applied with a voltage of 10V, a simulationwas made. When the film thickness of the second insulating film was 100nm and 200 nm,respectively, the S-value was 0.25 V/dec. Consequently, itis possible to reduce the value lower than the S-value (0. 26 V/dec) ofthe N-channel type TFT, which was assumed as an ordinary constitution.Accordingly, it is preferred that the film thickness of the secondinsulating film is 100 nm or more. In the above-described simulation, itwas assumed that the film quality of the semiconductor layer of the TFTof ordinary constitution and that of the semiconductor layer of the TFTaccording to the invention were the same. According to the invention, atthe same time when the laser beam is irradiated, when the double-layeredsemiconductor is fused, since the absorbed heat is held each other, theperiod of cooling time of the fused silicon get longer compared to thecase that the single-layered semiconductor is fused. As a result, asemiconductor film excellent in the crystalinity can be obtained.

[0211] According the invention, since the area occupied by a pluralityof TFTs can be reduce largely, in addition to that it is possible towiden the margin for layout, each pixel size can be made further smallerresulting in a light-emitting device capable of high precise display.Further, since the area occupied by the plurality of TFTs can be reducedlargely, in particular, by providing a plurality of TFTs to one pixel,when such a constitution that the area displayed of the light-emittingdevice is reduced is adopted, the invention is effective.

[0212] Furthermore, the Embodiment 2 may be combined appropriately withthe Embodiment 1. Accordingly, when the pixel section and the drivecircuit are formed on the same substrate, it is possible to miniaturizethe pixel size owing to the Embodiment 2 and to miniaturize the drivecircuit size owing to the Embodiment 1.

[0213] Embodiment 3

[0214] Hereinafter, a typical TFT, to which the invention is applied,and the manufacturing method thereof will be shown in FIG. 4; and FIG. 5shows an example of a liquid crystal display device to which theinvention is applied. In the Embodiments 1 and 2, examples, in which aplurality of TFTs having different constitution is formed respectively,were shown; in the Embodiment 3, a TFT having a plurality of channelforming areas will be described as an example.

[0215] First of all, on a substrate 70 having an insulated surface, afirst insulating film 72, which will become a base insulating film, isformed. As for the first insulating film 72, a single or double layeredinsulating film comprised of silicon as the major component is formed.Although not shown in the figures, in this case, the first insulatingfilm 72 is formed into a double-layered constitution. AS the lower layerof the first insulating film 72, a silicon nitride/oxide film(composition ratio: Si=32%, O=27%, N=24%, H=17%) manufactured using rawmaterial gases of SiH₄, NH₃ and N₂O is formed 50 nm (preferably 10-200nm) in thickness in the manner of plasma CVD, at a film formingtemperature of 400° C. Next, after rinsing the surface with ozoneliquid, the oxidized film on the surface is removed with dilutehydrofluoric acid (1/100 diluted). Then, a silicon nitride/oxide film(composition ratio Si=32%, O=59%, N=7%, H=2%), which is manufacturedusing raw material gases SiH₄ and N₂O, is laminated 100 nm (preferably50-200 nm) in thickness to form the upper layer of the first insulatingfilm 72 in the manner of plasma CVD at a film forming temperature 400°C. Further, without releasing into atmosphere, a first semiconductorfilm (in this case, amorphous silicon film) having amorphous structureis formed 54 nm (preferably 25-200 nm) in thickness in the manner ofplasma CVD using film forming gas SiH₄ at a film forming temperature of300° C.

[0216] Next, a mask of resist is formed, and is subjected to an etchingtreatment to form a first semiconductor layer 73 into a desiredconfiguration, which is isolated like an island. After forming the firstsemiconductor layer 73, the mask of resist is removed.

[0217] Next, at the same time removing the oxidized film using anetchant containing hydrofluoric and rinsing the surface of the siliconfilm, a second insulating film 74 comprised of silicon as the majorcomponent, which will finally become a layer of the gate insulatingfilm. In this case, a silicon nitride/oxide film (composition ratioSi=32%, O=59%, N=7%, H=2%) is formed 50 nm (preferably 1 nm-200 nm) inthickness in the manner of plasma CVD.

[0218] Next, a second semiconductor film 75 having amorphous structureis formed with a film thickness within the range of 25-200 nm. Althoughthe materials for the first semiconductor film and the secondsemiconductor film are not particularly specified, preferably, usingsilicon or silicon germanium (Si_(x)Ge_(1−x)(X=0.0001-0.02)) alloy orthe like, the films are formed by known means (spattering, LPCVD, plasmaCVD or the like). The material and film thickness of the secondsemiconductor film may be different from those of the firstsemiconductor film.

[0219] Next, laser beam is irradiated to crystallize both of theabove-described two layers of semiconductors (FIG. 4A). In this case,the second harmonic (532 nm) or the third harmonic (355 nm), which isoutput from an YVO₄ laser of 10 W output continuous oscillation, isapplied. Preferably, the laser beam is reformed into an elliptical format the surface to be irradiated by means of an optical system, and isirradiated to the first semiconductor layer having amorphous structureand the second semiconductor film having amorphous structure. At thistime, the energy density of approximately 0.01-100 MW/cm² (preferably0.1-10 MW/cm²) is needed. The laser beam is irradiated while shiftingthe semiconductor film with respect thereto at a speed of approximately0.5-2000 cm/s. By irradiating the laser beam to the first semiconductorlayer 73 having amorphous structure and the second semiconductor film 75having amorphous structure, since the absorbed heat is held respectivelyand the period of cooling time is elongated, it is possible to grow intoa large size crystal. That is to say, it is possible to obtain asemiconductor film, which has a better crystalinity than the case thatan amorphous silicon film of single layer is crystallized by means ofthe laser beam of continuous oscillation.

[0220] After adding metal element (typically nickel), which acceleratesthe crystallization of the silicon, to the second semiconductor layer,the above-described laser beam may be irradiated from the rear-face sidethereof passing through the substrate. It is preferred that, in the casethat the metal element is added, the film thickness of the secondinsulating film is 10 nm or more, and, a gettering processing is carriedout in a later step to remove or reduce the same from the secondsemiconductor layer.

[0221] Further, if necessary, after carrying out the above-describedirradiation of the laser beam from the surface (second semiconductorlayer) side, the above-described irradiation of the laser beam may becarried out again passing through the substrate from the rear face(first semiconductor layer) side. When the crystallization is carriedout by irradiating the laser beam from the front-face side and therear-face side, the wavelength range of the laser beam is notparticularly specified. For example, an excimer laser of 400 nm inwavelength may be used.

[0222] Next, after carrying out the above-described patterning of thesecond semiconductor film, the surface of the second semiconductor layer77 is rinsed. By completing the steps up to this point, a sectional viewshown in FIG. 4B is obtained. Then, a third insulating film 78 comprisedof a single or laminated layer of an insulating film of silicon as themajor component is formed. The third insulating film comprised of anoxidized film may be formed on the surface only of the secondsemiconductor layer by means of thermal oxidization. The thirdinsulating film 78 will become finally a layer of gate insulating film.The film thickness of the third insulating film 78 is appropriatelyselectable within the range of 50 nm-200 nm.

[0223] Next, a first conductive film is formed, and an etching iscarried out using a mask to form a first electrode 71, which willfinally become a gate electrode. Then, an impurity element (P, As or thelike), which imparts N-type to the semiconductor, is added using thefirst electrode 71 as a mask (FIG. 4C). By appropriately setting thedoping conditions in accordance with the depth from the surfacerespectively, a desired impurity density can be added respectively tothe first semiconductor layer and the second semiconductor layer, whichare disposed at a different depth respectively. In this case,phosphorous is added to the second semiconductor layer 77 and the firstsemiconductor layer 76 in the manner of ion doping to form N-typeimpurity areas 80-83 in a manner of self-aligning. When the secondinsulating film 74 is relatively thin in thickness, the above can beachieved by one doping. Before carrying out the doping, the thirdinsulating film 78 may be subjected to a dry etching to remove the sameexcluding only the portion where overlaps with the first electrode 71.The second semiconductor layer is exposed and the impurity element maybe added thereto. Furthermore, when the selective ratio between thesecond semiconductor layer and the second insulating film is large,before and after carrying out the doping, the first semiconductor layermay be exposed excluding the portion where overlaps with the secondsemiconductor layer in the second insulating film by means of dryetching. When the first semiconductor layer and the second semiconductorlayer have been exposed, the latter step; i.e., the step in whichcontact holes reaching to the first semiconductor layer are formed canbe carried out easily.

[0224] Next, in order to activate the added impurity element, heattreatment and strong light irradiation from a lamp light source or laserbeam irradiation are carried out. Also, two layers may be activatedsimultaneously using a laser beam, which passes through the secondsemiconductor layer. When second harmonic-fourth harmonic are used forthe activation using a solid-state laser (YAG laser, YVO₄ laser, YLFlaser, or full-solid infrared laser of semiconductor laser excitation,or the like), which is capable of continuous oscillation, approximately0.01-100 MW/cm² (preferably, 0.01-10 MW/cm²) is required. Further, theirradiation is carried out at a speed of approximately 0.5-2000 cm/swhile shifting the semiconductor film relatively with respect to thelaser beam. Furthermore, since there is no wiring or the like at thelower side of the double-layered, it is desired that by irradiatingstrong light or laser beam from the rear-face side or both sides of therear-face side and the front-face side. When the activation is carriedout by irradiating the laser beam from the front-face side and therear-face side, the wavelength range of the laser beam is notparticularly specified. Also, with the activation, it is possible torestore plasma damages to the insulating film, which will become thegate insulating film and plasma damages to the boundary between theinsulating film, which will become the gate insulating film, and thesemiconductor layer.

[0225] Next, an interlayer insulating film 84 is formed and is subjectedto hydride treatment. And then, contact holes, which reach the impurityareas 80-83, are formed using a mask. When the enough selective ratio isprovided, each contact hole may be formed simultaneously; or may beformed separately; or may be formed step-by-step. The contact holes,which reach to the impurity areas 82, 83 of the second semiconductorlayer 77, are formed in the area inner than the area where the contactholes, which reach the impurity areas 80, 81 of the first semiconductorlayer 76. In This case, in order to be understood easily, in thesectional view, the contact holes are aligned on a horizontal line.However, it is not particularly specified, but the contact holes may beformed in a desired area by appropriately changing the configuration ofthe respective semiconductor layers. Next, a second conductive film isformed using a mask to form wirings 85-87 that electrically connects tothe impurity areas 80-83 respectively (FIG. 4D1).

[0226] By carrying out the above-described steps, a TFT, which has thefirst electrode 71 as the gate electrode and a plurality of channelforming areas 88, 89 on the different layers, can be formed. Since acommon gate electrode is provided, and being formed in a manner ofself-aligning, it is possible to form the same channel length L. The TFTincludes the source area 83, the drain area 81 and the impurity areas80, 82 connected via the connection electrode 85. That is to say, theactive layers of the TFT is such constituted so as to be includedseparately on the different layer respectively. The direction of thecarrier flow in the channel forming area 88 is opposite to the directionof the carrier flow in the channel forming area 89.

[0227]FIG. 4D2 shows an example of a top view. The sectional view takenalong the chain line A-A′ in FIG. 4D2 corresponds to FIG. 4D1. It isneedless to say that the invention is not limited to the top view.

[0228]FIG. 4D3 shows an example of an equivalent circuit diagram.Referring to the equivalent circuit diagram, although the equivalentcircuit is substantially the same as the conventional double gatestructure, since the distance between each of the channel forming areas88, 89 and the gate electrode 71 is different from each other, the sameis different from the conventional double gate constitution. Further,since it is not necessary to dispose the gate electrodes in parallel, itis possible to miniaturize the occupied area than that of the TFT havinga conventional double gate constitution. Even when the semiconductorlayer of the upper side is in the conductive state being applied with avoltage to the gate electrode 71, unless the semiconductor layer of thelower side is not in the conductive state, the TFT as a whole does notgets into the ON-state. Accordingly, actual gate insulating film becomesa combination of the third insulating film 78 and the second insulatingfilm 74. By adapting the film thickness of an actual gate insulatingfilm, it is possible to appropriately set the OFF-current value and thethreshold. Additionally, it is understandable that also the channelforming area 89 of the upper side functions as a part of the gateinsulating film. By constituting such TFT as described above, it ispossible to reduce the OFF-current value and a current leak.

[0229] In this case, although such a constitution that, by forming thesecond insulating film thin, ON/OFF control is made by applying avoltage to the semiconductor layer of the lower side, is adopted, byadopting such a constitution that the second insulating film is formedthicker, or using a material which has an extremely small permittivity,it is possible to make the semiconductor layer of the lower sidefunction as a resistance element.

[0230]FIG. 5 illustrates an example of liquid crystal display device towhich the above-described TFT is applied. For the same portions in FIG.5, which are the same as those in FIG. 4, the same reference numeralsare used.

[0231] In the pixel section of a active matrix type liquid crystaldisplay device, a TFT (pixel TFT) is provided to each of several hundredthousands to several million pixels, and each of the pixel TFTs isprovided with a pixel electrode.

[0232]FIG. 5A shows a sectional view of a switching element and theperiphery thereof, which are disposed in a pixel of an active matrixsubstrate; and FIG. 5B shows a top view thereof. Points different fromFIG. 4A are that, a pixel electrode 90 is provided to a drain wiring 86that connects to the semiconductor layer of the lower layer; the drainwiring 86 is overlapped with the gate wiring 71 with fourth insulatingfilm 84 sandwiched therebetween. In this case, it is an active matrixsubstrate which is used as a transmission type liquid crystal displaydevice, in which transparent conductive film (ITO(indium tin oxidealloy), an indium zinc oxide alloy (In₂O₃—ZnO), a zinc oxide(ZnO) or thelike) is used as the pixel electrode 90. A holding capacity is comprisedof the drain wiring 86 and the gate wiring 71 using the fourthinsulating film 84 as the dielectric.

[0233] In the Embodiment 3, although an example of a transmission typeliquid crystal display device will be described, when a material (Ag, Alor the like), which has a reflectivity, is used as a material to formthe pixel electrode, it is possible to manufacture a reflection typeliquid crystal display device.

[0234] After obtaining an active matrix substrate, in which TFTs shownin FIG. 5A are disposed in a matrix-like configuration, an orientationfilm is formed on the active matrix substrate, and is subjected to arubbing processing. In this case, before forming the orientation film,pole-like spacers are formed at desired positions for maintaining thedistance of the substrate by patterning an organic resin film comprisedof an acrylic resin film or the like. In place of the pole-like spacer,sphere-like spacers may be splayed all over the substrate surface.

[0235] Next, an opposed substrate is prepared. On the opposed substrate,a color filter, in which a coloring layer and a light -shielding layerare disposed corresponding to each pixel. Also, the light-shieldinglayer is provided to the drive circuit portion. A planarizing film,which covers the color filter and the light-shielding layer, isprovided. Then, on the planarizing film, an opposed electrode comprisedof a transparent conductive film is formed in the pixel section, and allover the opposed substrate, an orientation film is formed, and the sameis subjected to a rubbing processing.

[0236] Then, the active matrix substrate and the opposed substrate arebonded with a sealing material. Filler is mixed in the sealing material,and two substrates are bonded while keeping an even distancetherebetween owing to the filler and the pole-like spacer. Next, liquidcrystal material is injected between both substrates and sealedperfectly by means of sealant. As for liquid crystal material, a knownliquid crystal material may be used. Thus, active matrix type liquidcrystal display device is completed.

[0237]FIG. 5C shows an equivalent circuit diagram of an active matrixtype liquid crystal display device. Although not shown in FIG. 5B, aholding capacity 92 is formed in another place. At the opposed substrateside, which sandwiches liquid crystal, an opposed electrode is providedto form a kind of capacitor 91, which uses the liquid crystal as thedielectric. It is adapted that a voltage to be applied to each pixel iscontrolled by means of switching function of the TFT, the liquid crystalis driven by controlling the charge to the capacitor, and thus bycontrolling the transmitting light, images are displayed.

[0238] The pixel TFT is comprised of an N-channel type TFT, which isformed by following the steps shown in FIG. 4, and the same, as theswitching element, applies a voltage to the liquid crystal to drive thesame. Since the liquid crystal is driven with AC current, a methodcalled as frame inversion drive is adopted in many cases. In thismethod, in order to reduce the power consumption, since an importantcharacteristic required to the pixel TFT is to reduce substantially theOFF-current value (drain current which flows when the TFT is in OFFoperation), the TFT according to the invention is useful for the pixelTFT.

[0239] According to the invention, it is possible to manufacture a TFT,of which OFF-current value is sufficiently small, in a small area. Also,the TFT shown in FIG. 4 comprises one gate electrode. Since it is notnecessary to dispose the gate electrodes in parallel, it is possible toform the occupied area smaller than that of the TFT of a conventionaldouble gate constitution. In the TFT of a conventional double gateconstitution, since two gate electrodes are disposed in parallel, thelength in the channel length direction requires, at least, the width fortwo gate electrodes and the width between the gate electrodes, theselengths were decided depending on the patterning accuracy. On the otherhand, according to the invention, at least, as for the length in thechannel length direction, only the width of one gate electrode isenough. As a result, according to the invention, since it is possible tolargely miniaturize the area occupied by the TFT, it is possible toenlarge the margin for layout, and in the transmission type liquidcrystal display device, it is possible to contribute to increase theaperture ratio.

[0240] Further, in the Embodiment 3, an example an N-channel type TFT ismanufactured by adding an N-type impurity element has been described.However, it is possible that, in place of the N-type impurity element,by adding a P-type impurity element, a P-channel type TFT also can bemanufactured.

[0241] Furthermore, in the Embodiment 3, an example of a top gate typeTFT has been described. However, in place of the gate electrode, whichis disposed above the second semiconductor layer, by disposing the gateelectrode below the first semiconductor layer, an inversed stagger typeTFT can be obtained.

[0242] Still further, the Embodiment 3 can be combined with theEmbodiment 1 and the Embodiment 2 appropriately.

[0243] The invention constituted as described above will be describedfurther in detail based on examples given below.

EXAMPLES Example 1

[0244] In Example 1, an example of concrete circuit constitution in anEL module is shown in FIG. 8 and FIG. 9.

[0245] In FIG. 8A, reference numeral 120 denotes a pixel section, and aplurality of pixels 121 is formed in a matrix configuration. Referencenumeral 122 denotes signal line drive circuits (source wiring side drivecircuits), and 123 denotes scanning line drive circuits (gate wiringside drive circuits).

[0246] An example of detailed constitution of the pixel 121 shown inFIG. 8A is shown in FIG. 2. Since the constitution shown in FIG. 2 isthe same as that of the above-described Embodiment 2, in this case,detailed description thereof will be omitted. The pixel 121 shown inFIG. 8 includes at least an OLED, which is a light-emitting element, aTFT, which is connected to the OLED to supply a current, a TFT, which isconnected to the TFT, a signal line Si (one of Sl-Sx), a scanning lineGj (one of Gl-Gy), a power supply line Vi (one of Vl-V_(x)). Further,although the pixel shown in FIG. 2 is not provided with any holdingcapacity, the holding capacity may be provided thereto. It is needlessto say that the pixel constitution is not limited to that shown in FIG.2.

[0247] In FIG. 8A, although the signal line drive circuits 122 and thescanning line drive circuits 123 are formed on the same substrate asthat of the pixel section 120, the invention is not limited to thatconstitution. A part of the signal line drive circuits 122 and thescanning line drive circuits 123 may be formed on a substrate differentfrom that of the pixel section 120 and be connected to the pixel section120 via a connector such as an FPC or the like. Also, in FIG. 8A, eachone signal line drive circuits 122 and scanning line drive circuits 123are provided, the invention is not limited that constitution. Thedesigner can appropriately decide the number of the signal line drivecircuits 122 and the scanning line drive circuits 123.

[0248] In this specification, the term “connection” means electricalconnection.

[0249] In FIG. 8A, signal lines Sl-Sx, power supply lines Vl-Vx andwirings for applying a voltage on scanning lines Gl-Gy are connected tothe pixel section 120. The number of the signal lines and the powersupply lines are not always the same. In addition to these wirings,other different wirings may be provided.

[0250] The power supply lines Vl-Vx are maintained at a predeterminedelectric potential. In FIG. 8A, although a constitution of alight-emitting device for displaying monochrome images, the inventionmay be a light-emitting device for displaying color images. In thatcase, the electric potential of the power supply lines Vl-Vx may not bemaintained at the same level, but the same may be changed based on thecorresponding colors.

[0251]FIG. 8B is a block diagram illustrating an example of a detailedconstitution of the signal line drive circuits 122 shown in FIG. 8A.Reference numeral 122 a denotes a shift register, 122 b denotes memorycircuits A, 122 c denotes memory circuits B, and 122 d denotesconstant-current circuits.

[0252] Clock signals CLK and start pulse signals SP are input to theshift register 122 a. Also, digital video signals are input to thememory circuits A 122 b, and latch signals are input to the memorycircuits B 122 c. Fixed signal currents Ic output from theconstant-current circuits 122 d are input to the signal line.

[0253] By inputting the clock signals CLK and the start pulse signals SPfrom a predetermined wiring to the shift register 122 a, timing signalsare generated. The timing signals are input to a plurality of latchesA(LATA_1-LATA-x) included in the memory circuits A 122 b. It may beconstituted so that the timing signals generated in the shift register122 a are buffered and amplified by means of a buffer or the like, andthen, be input respectively to the plurality of latches A(LATA_1-LATA_x) included in the memory circuits A 122 b.

[0254] When the timing signals are input to the memory circuits A 122 b,synchronizing to the timing signals, digital video signals for 1 bit,which are input to a video signal line, are written on each of theplurality of latches A(LATA_1-LATA _x) in order and stored therein.

[0255] In this case , when the digital video signals are input to thememory circuits A 122 b, although the digital video signals are input tothe plurality of latches A (LATA_1-LATA_x) included in the memorycircuits A 122 b in order, the invention is not limited to thatconstitution. So-called slit drive, in which latches of a plurality ofstages included in the memory circuits A 122 b are divided into severalgroups, and the digital video signals are input to each group parallellyand simultaneously, may be carried out. In this case, the number of thegroups is named as number of splits. For example, latches are dividedinto groups based on four stages; it is expressed as “four-split drive”.

[0256] The period of time until every writing of digital video signalsto the latches of all stages in the memory circuits A 122 b hascompleted is named as “line period”. Actually, there may be a case thata period, in which the period of horizontal retrace is added to theabove-described line period, is included in the line period.

[0257] After 1 line period has completed, latch signals are supplied toa plurality of latches B(LATB-1-LATB_x) included in the memory circuitsB 122 c via a latch signal line. At this time, the digital videosignals, which are stored in the plurality of latches A(LATA_1-LATA_x)included in the memory circuits A 122 b, are written at a time on theplurality of latches B(LATB_1-LATB-x) included in the memory circuits B122 c and stored therein.

[0258] To the memory circuits A 122 b, which has transmitted the digitalvideo signals to the memory circuits B 122 c, based on the timingsignals from the shift register 122 a, the next digital video signalsfor 1 bit are written in order.

[0259] During 1 line period of the second turn, the digital videosignals written and stored in the memory circuits B 122 c are input tothe constant-current circuits 122 d.

[0260]FIG. 9A illustrates a more detailed constitution of a currentsetting circuit C1. The current setting circuits C2-Cx also have thesame constitution. Further, FIG. 9B shows equivalent circuits of the SWand the Inb in the FIG. 9A. It is possible to apply the invention to theSW and the Inb, and the area occupied by the drive circuit can bereduced. When the invention is applied to, it is preferred to align thesame to the constitution of the pixel section. In FIG. 2, since thelower side is an N-channel type TFT and the upper side is a P-channeltype TFT, likewise, the SW and the Inb are also made into the sameconstitution, and the size thereof is adapted to a size in accordancewith the SW and the Inb respectively. As for the Inb, an example ofapplication will be described in Embodiment 1.

[0261] The current setting circuit C1 includes a constant-current source131, four transmission gates SW1-SW4 and two inverters Inb1, Inb2. Thepolarity of the transistor 130 included in the constant-current source131 is the same as the polarity of the transistor included in the pixel.

[0262] The switching of SW1-SW4 is controlled by the digital videosignals output from the LATB-1 included in the memory circuits B 122 c.The digital video signals input to SW1 and SW3 and the digital videosignals input to SW2 and SW4 are inverted by Inb1 and Inb2. Accordingly,when SW1 and SW3 are ON, SW2 and SW4 are OFF; when SW1 and SW3 are OFF,SW2 and SW4 are ON.

[0263] When SW1 and SW3 are ON, a current Ic of predetermined value not0 is input from the constant-current source 131 to the signal line Slvia SW1 and SW3.

[0264] On the contrary, when SW2 and SW4 are ON, the current Ic from theconstant-current source 131 is allowed to flow to the ground via SW2.Also, a power potential of power supply line Vl-Vx is given to thesignal line Sl via SW4 resulting in Ic≈0.

[0265] Referring to FIG. 8B again, the above-described operation iscarried out simultaneously within 1 line period in every current settingcircuit (Cl-Cx) included in the constant-current circuits 122 d.Accordingly, the values of the signal current Ic to be input to everysignal line are selected based on the digital video signals.

[0266] Next, the constitution of the scanning line drive circuits 123will be described.

[0267] The scanning line drive circuits 123 have a shift register and abuffer respectively. Also, depending on the case, a level shifter may beincluded.

[0268] In the scanning line drive circuits, when clock CLK and startpulse signal SP are input to the shift register, timing signals aregenerated. The generated timing signals are buffered and amplified inthe buffer, and are supplied to the corresponding scanning linerespectively. It is possible to apply the invention to the buffercircuit and the area occupied by the drive circuit can be reduced.

[0269] To the scanning line, gates of transistors for 1 pixel line areconnected. And since it is necessary to turn on the transistors of thepixels for 1 line simultaneously, a buffer capable of flowing a largecurrent is used.

[0270] In place of the shift register, for example, another circuit suchas a decoder circuit, which is capable of selecting the scanning line,may be used.

[0271] The voltage of each scanning line may be controlled by aplurality of scanning line drive circuits corresponding to each scanningline, or, one scanning line drive circuit may control the voltage ofseveral scanning lines or of all scanning lines.

[0272] It is needless to say that the signal line drive circuits 122 andthe scanning line drive circuits 123 that drive the semiconductor devicehaving the OLED according to the invention are not limited to theconstitution described herein.

[0273] According to Example 1, by applying Embodiment 2 to theabove-described pixel constitution, it is possible to largely reduce thearea, which is occupied by a plurality of TFTs in one pixel of the pixelsection. Additionally, by applying Embodiment 1 to a part or all of theCMOS circuits in the above-described drive circuits, it is possible tolargely reduce the area, which is occupied by the CMOS circuits in thedrive circuits. Further, according to the Example 1, it is possible tocombine the Embodiment 1 and the Embodiment 2 appropriately with eachother.

[0274]FIG. 10 is an external view illustrating an example of an ELmodule, which is completed by applying Embodiment 1 and Embodiment 2.FIG. 10A is a top view of a module having an OLED, i.e., an EL module.FIG. 10B is a sectional view taken along the line A-A′ in FIG. 10A. On asubstrate 200 (for example, a glass substrate, a crystallized glasssubstrate or, a plastic substrate or the like) having a insulatedsurface, a pixel section 202, source-side drive circuits 201 and agate-side drive circuit 203 are formed. The source-side drive circuits201 correspond to the signal line drive circuits 122 in FIG. 8, thegate-side drive circuits 203 correspond to scanning line drive circuits123 in FIG. 8 and the pixel section 202 corresponds to the pixel section120 in FIG. 8, respectively. These pixel section and drive circuits canbe obtained by following the above-described Embodiment 1 or Embodiment2.

[0275] Reference numeral 218 denotes a sealing material and 219 denotesa protection film. The pixel section and the drive circuit section arecovered by the sealing material 218, the sealing material is covered bythe protection film 219; and further sealed by a cover material 220using an binding material. As for the cover material 220, a basematerial of any composition such as plastic, glass, metal, ceramic orthe like may be used. Also, the configuration of the cover material 220and the configuration of the support are not particularly limited to;any material having plane surface, curved surface or flexibility orfilm-like configuration is usable. In order to withstand against anydeformation due to heat, an external force or the like, as for the covermaterial 220, it is desired to use the same material as the substrate200, such as a glass substrate. In Example 1, a concave configuration(3-10 μm in depth) shown in FIG. 10 is formed by means of sandblast orthe like. It is desired to further process to form a concave portion(50-200 μm in depth) for disposing a drying agent 221. Furthermore, inorder to protect an EL layer 216, a space between the substrate 200 andthe cover material 220 may be filled with silicon oil. Further, in thecase that the EL module is manufactured in a multi-substrate processingmethod, after the substrate and the cover material are bonded withtogether, each EL module may be cut off using CO₂ laser or the like sothat the edge faces thereof are aligned with each other.

[0276] Although, not shown herein in the drawings, in order to preventany background from being reflected due to reflection of a used metallayer (in this case, cathode or the like), a circular polarizing meanscalled as circular polarizing plate comprised of a phase shift film (λ/4plate) or a polarizing plate may be provided to the substrate 200.

[0277] Reference numeral 208 denotes a wiring, which transmits signalsto be input to the source-side drive circuits 201 and the gate-sidedrive circuits 203, and the same receives video signals and clocksignals from an FPC (flexible printed circuit) 209, which is an externalinput terminal. According to the Example 1, the light-emitting devicemay be driven in a digital or analog manner; and the video signals maybe digital signals or analog signals. Further, although not shown herein the drawings, a printed wiring board (PWB) may be mounted to thisFPC. The light-emitting device set forth in this specification should beunderstood that not only the light-emitting device main body, but alsothe same in a state that a FPC or a PWB is mounted thereto. Further,although it is also possible to form a complicated integrated circuit(CPU, controller or the like) on the same substrate as that of the pixelsection and the drive circuit, it is difficult to manufacture the sameusing a small number of masks. Accordingly, it is preferred that an ICchip equipped with a CPU, a controller or the like is mounted in amanner of COG (chip on glass), TAB (tape automated bonding) or wirebonding.

[0278] Next, referring to FIG. 10B, the sectional constitution will bedescribed below. On the substrate 200, an insulating film 210 is formed,and above the insulating film 210, the pixel section 202 and thegate-side drive circuits 203 are formed. The pixel section 202 comprisesa current controlling TFT 211 a, a pixel electrode 212 b, which iselectrically connected to the drain thereof, and a plurality of pixelsincluding a switching TFT 211 b. However, the constitution of a pixel isnot limited to the pixel constitution described above (two TFTs in onepixel), but a plurality of TFTs and circuits may be built in one pixel.Various circuits provided in the gate-side drive circuits 203 are formedusing a CMOS circuit, in which an N-channel type TFT 213 and a P-channeltype TFT 214 are combined with each other.

[0279] According to the Example 1, an N-channel type TFT of inversedstagger type is used as the switching TFT 211 b; while, a P-channel typeTFT of top gate type is used as the current controlling TFT 211 a.However, the invention is not limited to that constitution. Theswitching TFT and the current controlling TFT may be the P-channel typeTFT or the N-channel type TFT. When the anode of the OLED is used as thepixel electrode, it is desired that the current controlling TFT is aP-channel type TFT; while, when the cathode of the OLED is used as thepixel electrode, it is desired that the current controlling TFT is anN-channel type TFT.

[0280] The pixel electrode 212 b, which is electrically connected to aconnection electrode 212 a, one impurity area of the current controllingTFT 211 a, is made to function as the anode of the OLED. Furthermore, atthe both ends of the pixel electrode 212 b, a bank 215 is formedrespectively; and on the pixel electrode 212 b, a cathode 217 of the ELlayer 216 and the OLED is formed.

[0281] The cathode 217 functions as the wiring, which is common to everypixel, as well, and is electrically connected to the FPC 209 via theconnection wiring 208. Since the smaller work function results in thehigher light-emitting efficiency, particularly, as for the material usedfor the cathode, it is desired to use an alloy material including Li(lithium), which is a one of alkaline metal. Further, the elementsincluded in the pixel section 202 and the gate-side drive circuits 203are all covered by the cathode 217, the sealing material 218 and theprotection film 219.

[0282] As for the sealing material 218, it is desired to use a material,which is transparent or semitransparent with respect to the visibleradiation. Also, as for the sealing material 218, it is desired to use amaterial, which does not allow moisture or oxygen to pass through aspossible. Further, the sealing material may not be providedparticularly.

[0283] Furthermore, it is desired that, after the OLED has beencompletely covered with the sealing material 218, as shown in FIG. 10,the protection film 219 comprised of single layer or laminated-layerselected from AlON film, AlN film, Al₂O₃ film, or DLC film is providedon the surface (exposed surface) of the sealing material 218.

[0284] By sealing the OLED with a protection film having theabove-described structure, it is possible to shut out the OLED from theexternal, and to prevent any substance such as moisture, oxygen or thelike, which accelerates deterioration due to the oxidation of the ELlayer, from coming in from the external. Accordingly, it is possible toobtain a highly reliable light-emitting device.

[0285] Furthermore, such a constitution that the cathode is used as thepixel electrode, and by building up the EL layer and the anode so as toemit light in the opposite direction shown in FIG. 10, may be adopted.To emit light toward the opposite direction, it is realized by formingthe cover material with a material, which allows light to transmit, andby providing a circular polarizing means to the cover material.

Example 2

[0286] In Example 2, an example, which has a pixel constitutiondifferent from that described in the Embodiment 1 and the Example 1, inparticular, memory element (SRAM) is incorporated into each pixel, willbe described. FIG. 11 shows an equivalent circuit diagram of one pixel.

[0287] Referring to FIG. 11, reference numeral 305 is a switching TFT.The gate electrode of the switching TFT 305 is connected to a gatesignal line 306, which is a one of the gate signal lines (Gl-Gn) thatinputs gate signals. One of the source area and the drain area of theswitching TFT 305 is connected to one of the source signal lines 307,which is one of the source signal lines (Sl-Sn) that inputs signals; andthe other one thereof is connected to the input side of a SRAM 308. Theoutput side of the SRAM 308 is connected to the gate electrode of acurrent controlling TFT 309.

[0288] Further, one of the source area and the drain area of the currentcontrolling TFT 309 is connected to a current supply line 310, which isone of the current supply lines (Vl-Vn); and the other one thereof isconnected to an OLED 311.

[0289] The OLED 311 is comprised of an anode, a cathode and an EL layer,which is disposed between the anode and the cathode. When the anode isconnected to the source area or the drain area of the currentcontrolling TFT 309; in other words, in the case that the anode is thepixel electrode, the cathode is the opposed electrode. On the contrary,when the cathode is connected to the source area or drain area of thecurrent controlling TFT 309; in other words, in the case that thecathode is the pixel electrode, the anode is the opposed electrode.

[0290] The SRAM 308 has two P-channel type TFTs and N-channel type TFTsrespectively; the source area of the P-channel type TFT is connected toVddh at the high voltage side, the source area of the N-channel type TFTis connected to the Vss at the low voltage side, respectively. OneP-channel type TFT and one N-channel type TFT make a pair; accordingly,two pairs of the P-channel type TFT and the N-channel type TFT includedin one SRAM.

[0291] The pair of the P-channel type TFT and the N-channel type TFT areconnected to each other via the respective drain areas. Also, the pairof the P-channel type TFT and the N-channel type TFT are connected toeach other via the respective gate electrodes. And in each of pairs, thedrain areas of the paired P-channel type TFT and N-channel type TFT aremaintained at the same electric potential as that of the gate electrodesof the another paired P-channel type TFT and N-channel type TFT.

[0292] The drain are as of one pair of P-channel type and N-channel typeTFTs are the input sides to which the input signals (Vin) are input;while, the drain areas of another pair of P-channel type and N-channeltype TFTs are the output sides to which output signals (Vout) areoutput.

[0293] The SRAM is adapted so as to hold the Vin and output the Vout,which are the inverted signals of the Vin. That is to say, when the Vinis Hi, the Vout results in the signals of Lo equivalent to Vss; while,when the Vin is Lo, the Vout results in the signals of Hi equivalent toVddh.

[0294] As described in Example 2, when a single SRAM is provided to apixel 304, since memory data in the pixel is held, in a state that mostexternal circuits have been shut down, a frozen frame can be displayed.Owing to this arrangement, smaller power consumption can be achieved.

[0295] It is possible to provide a plurality of SRAMs to the pixel. Whena plurality of SRAMs is provided thereto, since a plurality of data canbe held; it is made possible to perform tone display in time-tone mode.

[0296] According to Example 2, by forming and integrating at least apair of P-channel type TFT and N-channel type TFT according toEmbodiment 1 or Embodiment 2, it is possible to miniaturize the areaoccupied by the SRAM 308. Additionally, it is possible to integrate apair of the switching TFT 305 and the current controlling TFT 309according to the Embodiment 2.

[0297] Although an example in which, in a light-emitting device havingan OLED, a SRAM is built in a pixel has been described here. In a liquidcrystal display device also, a SRAM may be built in a pixel. By forminga SRAM, of which occupied area has been miniaturized according to theinvention, in a pixel, the aperture ratio of a liquid crystal displaydevice is increased largely.

[0298] Although, an example, in which the area occupied by a SRAM isminiaturized, has been described here; likewise, it is possible tominiaturize other memory elements, for example, the area occupied by aDRAM also can be miniaturized and built in a pixel.

[0299] The Example 2 can be combined with the Example 1, the Embodiment1, the Embodiment 2 or the Embodiment 3 freely.

Example 3

[0300] In the Example 3, an example of a pixel, which has aconfiguration different from that shown in the Example 1 and Example 2,is shown in FIG. 12.

[0301] The pixel shown in FIG. 12A has TFTs 411, 412, 413, 414, aholding capacity 415 and an OLED (light-emitting element) 416.

[0302] According to Example 3, four TFTS, 411, 412, 413 and 414 providedin a pixel are integrated using the Embodiment 1 or Embodiment 2 tominiaturize the area occupied thereby. Even when the TFTs areintegrated, the driving method is the same. The constitution of thepixel and the driving method of the OLED will be described below.

[0303] In the TFT 411, the gate is connected to a terminal 418, one endsof the source and the drain are connected to a current source 417; theother ends thereof are connected to the drain of the TFT 413. In the TFT412, the gate is connected to the terminal 419, one ends of the sourceand the drain are connected to the drain of the TFT 413; the anotherends thereof are connected to the gate of the TFT 413. The TFT 413 andthe TFT 414 are connected to each other and both of the sources thereofare connected to the terminal 420. The drain of the TFT 414 is connectedto the anode of the OLED 416; the cathode of the OLED 416 is connectedto the terminal 421. The holding capacity 415 is provided so as to holdthe voltage between the gate and the source of the TFTs 413 and 414. Theterminals 420, 421 are supplied with a predetermined voltage from thepower supply respectively, and each of them has a voltage difference.

[0304] After the TFTs 411, 412 turns ON due to the voltage given to theterminals 418, 419, the drain current of the TFT 413 is controlled bythe current source 417. In this case, since the gate and the drain areconnected to each other, the TFT 413 operates in a saturated area. Inthis case, the drain current of the TFT 413 varies depending on the gatevoltage. Also, since the gate and the source of the TFT 413 and the TFT414 are connected to each other, the gate voltage of the TFT 414 is heldat the same voltage as the gate voltage of the TFT 413.

[0305] Accordingly, the drain currents of the TFT 413 and the TFT 414are resulted in the proportional relationship. Particularly, when theelectrical characteristic values of the TFTs are the same, the draincurrents of the TFT 413 and the TFT 414 are resulted in the same. Thedrain current, which flows to the TFT 414, is supplied to the OLED 416;the OLED 416 emits light at a luminance corresponding to the magnitudeof the drain current. Owing to the voltage given to the terminals 418,419, even after the TFTs 411, 412 have turned OFF, while the gatevoltage of the TFT 414 is held by the holding capacity 415, the OLED 416continues to emit light.

[0306] As described above, the pixel shown in FIG. 12A includes meansfor converting a current supplied to the pixel into a voltage andholding the same; and means for flowing a current of a magnitudecorresponding to the held voltage to the light-emitting element.

[0307] A pixel constitution different from that shown in FIG. 12A isshown in FIG. 12B. The pixel shown in FIG. 12B includes TFTs 431,432,433and 434, a holding capacity 435 and an OLED 436.

[0308] According to the Example 3, four TFTs of 431, 432, 433 and 434provided to one pixel are integrated using the Embodiment 1 or theEmbodiment 2 to miniaturize the area occupied thereby. Even when theTFTs are integrated, the driving method thereof is the same. Theconstitution of the pixel and the driving method of the OLED will bedescribed below.

[0309] In the TFT 431, the gate is connected to a terminal 438, one endsof the source and the drain are connected to a current source 437, Theother ends thereof are connected to the source of the TFT 433. In theTFT 434, the gate is connected to the terminal 438, one of the sourceand the drain is connected to the gate of the TFT 433, the other endthereof is connected to the drain of the TFT 433. In the TFT 432, thegate is connected to the terminal 439; one of the source and the drainis connected to the terminal 440 and the other is connected to thesource of the TFT 433. The drain of the TFT 434 is connected to theanode of the OLED 436; the cathode of the OLED 436 is connected to theterminal 441. The holding capacity 435 is provided to hold a voltagebetween the gate and the source of the TFT 433. A predetermined voltageis applied to the terminals 440, 441 from the power supply and each ofthem holds a voltage difference.

[0310] After the TFTs 431 and 434 turn ON due to the voltage given tothe terminal 438 and the TFT 432 turns OFF due to the voltage given tothe terminal 439, the drain current of the TFT 433 is controlled by thecurrent source 437. Since the gate and the drain are connected to eachother, the TFT 433 operates in a saturated area. In this case, the draincurrent of the TFT 433 varies depending on the gate voltage.

[0311] The drain current, which flows to the TFT 433, is supplied to theOLED 436, and the OLED 436 emits light at a luminance corresponding tothe drain current.

[0312] After the TFTs 431, 434 are turned OFF owing to the voltage givento the terminal 438, the TFT 432 is turned ON owing to the voltage givento the terminal 439. While the gate voltage of the TFT 433 is held bythe holding capacity 435, the OLED 436 continues to emit light at thesame luminance as that when the TFTs 431, 434 are ON.

[0313] As described above, the pixel shown in FIG. 12B includes meansfor converting a current supplied to the pixel into a voltage andholding the same, and for flowing the current of a magnitudecorresponding to the held voltage to the light-emitting element.

[0314] Even when the threshold of the TFT or the characteristics of theON-current or the like is uneven among the pixels, the magnitude of thecurrent, which flows to the OLED is controlled by the current source,the above-described pixel shown in FIGS. 12A and 12B can preventdispersion of luminance of the OLED from occurring among the pixels.

[0315] The Example 3 can be combined with the Example 1. In place of thepixel constitution of the Example 1, the pixel constitution shown inFIGS. 12A and 12B may be used.

[0316] As described above, the invention can be applied to withoutdepending on the constitution of the pixel or the driving method of theOLED.

Example 4

[0317] In the Embodiment 1, an example, in which two gate electrodes areprovided to form a CMOS circuit, has been described. According to theExample 4, FIG. 13 shows an example, in which a CMOS circuit is formedusing one gate electrode.

[0318] Steps that are the same as those of the Embodiment 3 will beomitted here. The portion in FIG. 13 that is the same as that of FIG. 4will be given with the same reference numeral used therein.

[0319] First of all, according to Embodiment 3, a state that is the sameas that shown in FIG. 4B is obtained (FIG. 13A).

[0320] Next, according to the Embodiment 3, a third insulating film of asingle layer or laminated-layer, which comprises an insulating film ofsilicon as the major component, and a first electrode 71 is formed. Or,by means of thermal oxidization, a third insulating film of an oxidizedfilm may be formed only on the surface of the second semiconductorlayer. The film thickness of the third insulating film is selectableappropriately within a range of 50 nm-200 nm.

[0321] Next, an etching is carried out using the first electrode 71 asthe mask to selectively remove the third insulating film excluding aportion where is overlapped with the first electrode 71, to form a thirdinsulating layer 503. However, although an example, in which the thirdinsulating layer is formed by carrying out the etching, is shown, it maynot be carried out. Then, an impurity element (boron) for impartingP-type in a manner of self-aligning is added to the partially exposedsecond semiconductor layer using the first electrode 71 as the mask toform impurity areas 501 and 502(FIG. 13B). In this case, since a highdensity doping is made using a relatively low acceleration voltage tothe exposed area, little P-type impurity element is added to the firstsemiconductor layer.

[0322] Next, an impurity element (phosphorous) imparting N-type in amanner of self-aligning is added using the first electrode 71 as themask to form impurity areas 504 a, 504 b, 505 a and 505 b (FIG. 13C). Inthis case, allowing the impurity element to pass through a secondinsulating film 74, a high density doping is made using a relativelyhigh acceleration voltage. In this case, although phosphorous is addedto the impurity areas 501 and 502 at a low density, since boron has beenadd at high density, the impurity areas 501 and 502 finally functionsatisfactorily as the source area or drain area of the P-channel typeTFT. Also, in the area where the depth from the surface is different dueto the second semiconductor layer thereabove; i.e., in the impurityareas 504 b and 505 b, the dopant is added at a low density forming anLDD area. Further, since the boron is small in atom size and is hard tobe activated after the addition, by giving a doping damage by means ofthe doping of the phosphorous to make second semiconductor layer beamorphous so as to be easily crystallized (activated) again in thelatter activation step.

[0323] Not being limited to the above-described doping order, afteradding the impurity element for imparting N-type first, the impurityelement for imparting P-type may be added.

[0324] Then, the second insulating film 74 is selectively removed usingthe second semiconductor layer as the mask, and the second insulatinglayer 506 is formed. It is important to form the second insulating layerunder such etching conditions that sufficient selective ratio betweenthe second insulating film and the second semiconductor layer isobtained; and the film thickness is the same as the second insulatingfilm. Although an example, in which the second insulating layer isformed by carrying out the etching, is described here, the same may notbe carried out.

[0325] Next, in order to activate the added impurity element, a heattreatment, an irradiation of a strong light from the lamp light source,or an irradiation of a laser beam is carried out. The activation of twolayers may be carried out simultaneously using the laser beam passingthrough the second semiconductor layer. When the second harmonic-fourthharmonic of the basic wave are used for activation using a solid-statelaser (YAG laser, YVO₄ laser, YLF laser or the like) capable ofcontinuous oscillation, approximately, 0.01-100 MW/cm² (preferably,0.01-10 MW/cm²) is necessary. The irradiation is carried out whileshifting the semiconductor film with respect to the laser beam at aspeed of approximately 0.5-2000 cm/s. Further, since no electrode or thelike resides in the lower layer of the double-layer, it is preferred toactivate the double-layered semiconductor layer simultaneously byirradiating the laser beam from the rear-face side thereof. Also, theirradiation of the strong light or laser beam may be carried out fromthe both sides of the rear-face side and the front-face side. When theirradiation of the laser beam is carried out from the front-face sideand the rear-face side to activate, the wavelength range of the laserbeam is not particularly specified. Further, with the activation, it ispossible to recover the plasma damage on the insulating film thatbecomes the gate insulating film and the plasma damage on the boundarybetween the insulating film that becomes the gate insulating film andthe semiconductor layer.

[0326] Then, after forming an interlayer insulating film 507 andcarrying out hydride treatment, contact holes that reach to therespective impurity areas are formed. In the case that the selectiveratio is obtained satisfactorily, although the contact holes may beformed simultaneously, each of them may be farmed separately. Thecontact holes, which reach to the impurity areas 501 and 502 of thesecond semiconductor layer, are formed inner side than the contactholes, which reach to the impurity area 504 a and 505 a of the firstsemiconductor layer. Then, wirings 508-510, which connect electricallywith the respective impurity areas, are formed (FIG. 13D1).

[0327] By carrying out the above-described steps, a P-channel type TFT500 of top gate constitution, which is comprised of the first electrode71 as the gate electrode; the third insulating layer 503 as the gateinsulating film; the source area 502, the drain area 501 and the channelforming area 512 sandwiched between the these areas as the active layer;the source wiring 510 connecting with the source area 502; and the drainwiring 509 connecting with the drain area 501, is completed.

[0328] Additionally, an N-channel type TFT of top gate constitution,which is comprised of the first electrode 71 as the gate electrode; thethird insulating layer 503 and the second insulating layer 506 as thegate insulating film; the source area 505 a, the drain area 504 a, theLDD areas 504 b and 505 b and the channel forming area 511, which issandwiched therebetween, as the active layer; and the source wiring 508,which connects with the source area 505 a; and the drain wiring 509,which connects with the drain area 504 a, is completed. Further, bycombining these TFTs complementally, a CMOS circuit can be manufactured.

[0329] Further, in the manufacturing process according to the invention,a CMOS circuit can be manufactured using 5 masks. Conventionally, whenmanufacturing CMOS circuits, which are positioned in parallel to eachother, total six masks were needed for semiconductor layer patterning,gate electrode patterning, a doping mask for the impurity element thatimparts N-type, a doping mask for the impurity element that impartsP-type, contact hole patterning, and wiring patterning. According to theinvention, by adding one mask for semiconductor layer and reducing twodoping masks, it is possible to largely miniaturize the area necessaryfor the CMOS circuit without increasing the number of the masks.

[0330] An example of a top view is shown in FIG. 13D2. The sectionalview taken along the chain line A-A in FIG. 13D2 corresponds to FIG.13D1.

[0331] Although the size of the first semiconductor layer is differentfrom that of the second semiconductor layer in order to establish thecontact therebetween, the configuration thereof is not particularlyspecified. The channel length L of the channel forming area 511 ofN-channel type TFT is the same as that of the channel forming area 512of P-channel type TFT.

[0332]FIG. 13D3 shows an example of an equivalent circuit diagram whenan inverter circuit, which is one of the examples of CMOS circuits.Referring the equivalent circuit diagram, although it is almost the sameas an ordinary CMOS circuit, but actually, the distances between therespective channel forming areas 511 and 512 and the gate electrodes 71are different from each other. Therefore, the equivalent circuit isdifferent from the ordinary CMOS circuit. Accordingly, in an N-channeltype TFT, the actual gate insulating film is comprised of the thirdinsulating layer 503 and the second insulating layer 506. Taking intothe fact into the consideration, by appropriately adapting the totalfilm thickness of these insulating layers within a range of 50 nm-200nm, it is possible to set the OFF-current value and the thresholdfreely. Additionally, it is understandable that the channel forming area512 also at the upper side functions as a part of the gate insulatingfilm. By adopting the constitution of the TFT as described above, it ispossible to reduce the OFF-current value and the current leak.

[0333] In this case, an example, in which an impurity element thatimparts N-type is added to the first semiconductor layer 76; and animpurity element that imparts P-type is added to the secondsemiconductor layer 77, has been described. However, an impurity elementthat imparts P-type may be added to the first semiconductor layer 76;and an impurity element that imparts N-type may be added to the secondsemiconductor layer 77.

[0334] Although the TFT shown in FIG. 13D1 is of a single gateconstitution, it is not limited thereto. A double gate constitutionhaving two channel forming areas, in which two gate electrodes areplaced in parallel into a plane configuration, or a multi-gateconstitution having a plurality of channel forming areas more than threemay be adopted.

[0335] Further, in this case, although an example of top gate type TFThas been described, in place of the gate electrode provided above thesecond semiconductor layer, by providing the gate electrode below thefirst semiconductor layer, an inversed stagger type TFT may be formed.

[0336] According to the Example 4, it is possible to largely miniaturizethe area occupied by the CMOS circuit. Accordingly, it is possible tominiaturize the drive circuit including the CMOS circuit.

[0337] Furthermore, the Example 4 may be combined with any of theEmbodiments 1-3 or the Embodiments 1-3 freely.

[0338] For example, when the Example 4 is combined with the Embodiment3, a CMOS circuit according to the Example 4 may be formed by formingthe pixel section and the drive circuit on the same substrate, and asfor the drive circuit, by forming the TFT of the pixel section with aTFT having a low OFF-current value, which has been described in theEmbodiment 3. In this case, it is possible to form, in the drivecircuit, a double-layered semiconductor layer overlapped with eachother; and, in the pixel section, a double-layered semiconductor layeroverlapped with each other. However, since is necessary to carry outdoping separately on the semiconductor layers of the upper layers in thedouble-layered semiconductor layers, another doping mask is required.

[0339] Furthermore, different kinds of TFTs may be formed selectively onthe same substrate. FIGS. 14A-C show an example of a manufacturingprocess. FIG. 14A corresponds to FIG. 4A shown in the Embodiment 3; thesame reference numerals are given to the same portions. As shown in FIG.14A, after irradiating laser beam, a patterning of the secondsemiconductor layer is carried out. In this case, a patterning, in whichin the area shown in the left side of the drawing, the secondsemiconductor layer is formed; in the right side thereof, the secondsemiconductor layer is not formed. Next, the third insulating film andthe first electrode are formed, and the third insulating film isselectively removed using the first electrode as the mask to form thethird insulating layer 503. Then, an impurity element for impartingN-type or P-type is doped, and to the semiconductor layer shown at theright side, only the impurity element that imparts N-type is added. TheTFT after this doping is shown in FIG. 14B, which corresponds to FIG.13c. In FIGS. 14B and C, the area shown at the left side is the same asthose shown in FIGS. 13C and D; the same reference numerals are given tothe same portions. Since the following steps are the same as the stepsfor obtaining the above-described state shown in FIG. 13C to FIG. 13D,the descriptions thereof are omitted here. Thus, as shown in FIG. 14C,in the left side area thereof, a CMOS circuit same as that shown in FIG.13D, is completed; at the same time, in the right side area thereof, aTFT 600 of double gate constitution is completed. The TFT 600 iscomprised of a gate electrode 605, a gate insulating film including thesecond insulating layer and the third insulating layer 503, a sourcearea or a drain area denoted by the reference numerals 603 and 604, anda source wiring or a drain wiring denoted by the reference numeral 601and 602.

Example 5

[0340] The Example 5 shows an example, in which a CMOS circuit having aconstitution different from that of the Embodiment 1, in FIG. 15. FIG.15A is a sectional view; FIG. 15B is a top view of the CMOS circuit. Inthe Example 5, the points different from the Embodiments are the factsthat: a first insulating film 712 is of a single layer, while a secondinsulating film is of a double-layered constitution (714 a, 714 b); thesize of the first electrode is different from that of the secondelectrode; and that an offset area 700 is formed. As for the pointsother than the above, the step and the constitution thereof are almostthe same as those in Embodiment 1, detailed descriptions will be omittedhere.

[0341] In the Embodiment 1, an example, in which a flattening processingis carried out on the first insulating film, have been described.According to the Example 5, the second insulating film is formed into adouble-layered constitution (714 a, 714 b), and then, the upper layer714 b of the second insulating film is formed by carrying out aflattening processing. As for the flattening processing, after forming acoating film (resist film or the like), etch back method orchemical-mechanical polishing (CMP) or the like may be used.

[0342] Further, according to the Example 5, the width of the firstelectrode 711 in the channel length direction is different from that ofthe second electrode 719. Since the second electrode 719 is used as thedoping mask, the channel length of the channel forming area 728 becomesL1 causing the channel length of the channel forming area 729 L2.Additionally, an offset area 700 is formed between the source area orthe drain area and the channel forming area 728. By forming the offsetarea 700, leak current is reduced.

[0343] Accordingly, the N-channel type TFT according to the Example 5 isan inversed stagger type TFT comprises a the first electrode 711 as thegate electrode, the channel forming area 728, the offset area 700connected with the channel forming area 728, the source area and thedrain area, a source wirings 726, 727 connected to the source area orthe drain area and a drain wiring 725.

[0344] Furthermore, the Example 5 can be combined with any of theEmbodiments 1-3, or Embodiments 1-4 freely.

Example 6

[0345] In the Example 6, an example, in which an impurity element forimparting P-type to the first semiconductor layer is added; while animpurity element for imparting N-type to the second semiconductor layeris added, is shown in FIG. 16.

[0346] In the Example 6, since the steps are almost the same as thoseshown in FIGS. 1A-D and the constitution also is almost the same, onlythe points different therefrom will be described below.

[0347] In the doping step, an impurity element (boron) for impartingP-type to the first semiconductor layer is added using a secondelectrode 819 as the mask; while, an impurity element (phosphorous orthe like) for imparting N-type to the second semiconductor layer isadded. By appropriately setting the doping conditions, the respectiveelements may be added. Also, according to the Example 6, the doping maybe carried out simultaneously. Since boron is smaller in atom radiusthan the phosphorous, boron is injected deeper into the film. When theelements are added using the same acceleration voltage, it is possibleto add the phosphorous to the second semiconductor layer, while, to addthe boron to the first semiconductor layer.

[0348] By following the steps in Embodiment 1 other than the dopingstep, a CMOS circuit shown in FIG. 16A is completed. A TFT 830, whichhas a top gate constitution comprised of the second electrode 819 as thegate electrode and the second semiconductor layer as the active layer,is an N-channel type TFT. While, The TFT, which has an inversed staggerstructure comprised of the first electrode 811 as gate electrode and thefirst semiconductor layer as the active layer, is a P-channel type TFT.Reference numeral 827 denotes a source wiring for the above-describedN-channel type TFT; 826 denote a source wiring for the above-describedP-channel type TFT.

[0349]FIG. 16B shows an example of a top view. A sectional view takenalong the chain line A-A′ in FIG. 16B corresponds to FIG. 16A.

[0350] The drain areas of these two TFTs are electrically connected tothe drain wiring 825. By combining with the above-described N-channeltype TFT 830 so as to be complementary each other, a CMOS circuit can beformed. FIG. 16C shows an example of an equivalent circuit diagram whena CMOS circuit is formed.

[0351] The Example 6 can be combined with the any of the Embodiments1-3, and Examples 1-5 freely.

Example 7

[0352] A drive circuit or a pixel section formed by implementing theinvention enables to achieve miniaturization, reduction in weight orhigh precision of various module (active matrix type liquid crystalmodule, active matrix type EL module and active matrix type EC module).That is to say, by implementing the invention, every electronicapparatus incorporated with those devices is completed.

[0353] As for examples of electronic apparatus, a video camera, adigital camera, a head mount display (goggle-type display), a carnavigation, a projector, a car stereo, a personal computer, a portableinformation terminal (mobile computer, cellular phone handset orelectronic book or the like) and the like are given. A part of thesesexamples are shown in FIG. 17-FIG. 19.

[0354]FIG. 17A shows a personal computer; a main body 2001, an imageinput section 2002, a display section 2003, a keyboard 2004 or the likeare included therein. According to the invention, since the area offrame rim is reduced, the entire size can be formed further compactly.Further, according to the invention, since it is possible to form thesize of each pixel further smaller, it is possible to achieve a highprecise display.

[0355]FIG. 17B shows a video camera; a main body 2101, a display section2102, an voice input section 2103, operation switches 2104, a battery2105, an image receiving section 2106 and the like are included therein.

[0356]FIG. 17C shows a mobile computer; a main body 2201, a camerasection 2202,an image receiving section 2203, an operation switch 2204,a display section 2205 and the like are included therein.

[0357]FIG. 17D shows a goggle type display; a main body 2301, displaysections 2302, arm sections 2303 and the like are included therein.

[0358]FIG. 17E shows a player that uses a recording medium (hereinafter,referred to as recording medium) stored with a program; a main body2401, a display section 2402, a speaker section 2403, a recording medium2404, operation switches 2405 and the like are included therein. Theplayer uses a DVD (Digital Versatile Disc), CD or the like as arecording medium to allow music listening, viewing movies, games andInternet.

[0359]FIG. 17F is a digital camera; a main body 2501, a display section2502, an eyepiece section 2503, operation switches 2504, an imagereceiving section (not shown in the Figure) and the like are includedtherein.

[0360]FIG. 18A is a front type projector; a projecting unit 2601, ascreen 2602 and the like are included therein. By applying the Example 3to a liquid crystal module 2808 constituting a part of the projector2601, the entire apparatus thereof can be achieved. According to theinvention, since it is possible to miniaturize the size of each pixel, ahigh precise display section can be achieved. Additionally, according tothe invention, it is possible to increase the aperture ratio.

[0361]FIG. 18B is a rear type projector; a main body 2701, a projectingunit 2702, a mirror 2703, a screen 2704 or the like are includedtherein. By applying the Example 3 to a liquid crystal module 2808constituting a part of the projecting unit 2702, the entire apparatuscan be achieved. According to the invention, since it is possible tominiaturize the size of each pixel, a high precise display section canbe achieved. Additionally, according to the invention, it is possible toincrease the aperture ratio.

[0362]FIG. 18C shows an example of the structure of the projecting units2601 and 2702 shown in FIG. 18A and FIG. 18B. The projecting units 2601and 2702 comprises a light source optical system 2801, mirrors 2802 and2804-2806, a diachronic mirror 2803, a prism 2807, a liquid crystalmodule 2808, a phase shift film 2809 and a projection optical system2810. The projection optical system 2810 comprises an optical systemincluding a projection lens. Although this example is exemplified by atriple-plate type, the same is not limited thereto, but for example, asingle type is also applicable. Further, in the light passes indicatedwith the arrows in FIG. 18C, an optical system such as an optical lens,a film having a polarizing function, a film for adapting phase shift, anIR film or the like may be provided appropriately by a practitioner ofthe invention.

[0363]FIG. 18D shows an example of the structure of the light sourceoptical system 2801 shown in FIG. 18C. In this example, the light sourceoptical system 2801 comprises a reflector 2811, a light source 2812,lens eyes 2813 and 2814, a polarizing conversion element 2815 and abeam-condensing lens 2816. Since the light source optical system shownin FIG. 18D is given as just an example, the same is not limitedthereto. For example, an optical system such as an optical lens, a filmhaving polarizing function, a film adapting phase shift, an IR film orthe like may provide to the light source optical system appropriately bya practitioner of the invention.

[0364] In the projector shown in FIG. 18, only a case that atransmission type electrooptical device is used is described. No exampleof application using a reflection type electrooptical device or ELmodule is given.

[0365]FIG. 19A shows a cellular phone handset; a main body 2901, anvoice output section 2902, an voice input section 2903, a displaysection 2904, an operation switch 2905, an antenna 2906, an image inputsection (CCD, image sensor or the like) 2907 and the like are includetherein. According to the invention, since the area of the frame rim isminiaturized, the entire size thereof can be formed further compact andlight weigh. Further, according to the invention, since it is possibleto form the size of each pixel further smaller, a high precise displaycan be achieved.

[0366]FIG. 19B shows a portable book (electronic book); a main body3001, display sections 3002 and 3003, a memory medium 3004, operationswitches 3005, an antenna 3006 and the like are included therein.

[0367]FIG. 19C shows a display; a main body 3101, a support base 3102, adisplay section 3103 and the like are included therein.

[0368] The display shown in FIG. 19C is a medium-small size or a largesize one; for example, having a screen size of 5-20 inch. To constitutea display section having this size, it is preferred that, using asubstrate of 1 m in edge length, a mass production in a manner ofmultiple products is carried out.

[0369] As described above, the application range of the invention isextremely wide, it is possible to apply to the manufacturing method ofelectronic apparatus in various field. Furthermore, the electronicapparatus according to the Example can be achieved by using anycombination of the Embodiments 1-3 and the Examples 1-6.

[0370] According to the invention, it is possible to realize a highperformance semiconductor device, in which a plurality of TFTs is highlyintegrated in three-dimension on a substrate having an insulated surfaceusing relatively small number of masks.

[0371] Also, according to the invention, it is possible to largelyminiaturize the area occupied by the CMOS circuit formed on thesubstrate having an insulated surface. Additionally, it is possible tocomplete the CMOS circuit according to the invention, of which occupiedarea is largely miniaturized, using six or seven masks used duringmanufacturing thereof.

[0372] Further, according to the invention, since the area occupied by aplurality of TFTs formed on a substrate having an insulated surface islargely miniaturized, it is possible to expand the layout margin.

[0373] Accordingly, in a display device exemplified by a light-emittingdevice or the like having liquid crystal display device or an OLED, inany of pixel section or drive circuit, or in both of the areas, it ispossible to miniaturize the occupied area (area occupied by a pluralityof TFT) in the horizontal direction.

[0374] Furthermore, according to the invention, since it is madepossible to make the size of each pixel further smaller, a high precisedisplay device can be realized. Still further, according to theinvention, since the occupied area of the plurality of TFT can belargely miniaturized, it is possible to provide a plurality of TFTs andvarious circuits in one pixel.

What is claimed is:
 1. A semiconductor device comprising: a firstelement which has a first semiconductor layer formed of a semiconductorfilm having crystal structure over an insulating surface; an insulatingfilm over said first semiconductor layer; and a second element which hasa second semiconductor layer formed of a semiconductor film havingcrystal structure on the insulating film, wherein, only said insulatingfilm is provided between said first semiconductor layer and said secondsemiconductor layer, a part of said first semiconductor layer isoverlapped with a part of said second semiconductor layer with saidinsulating film sandwiched therebetween.
 2. A device according to claim1, wherein said first element and said second element is selected fromthe group consisting of an N-channel type TFT, a P-channel type TFT, amemory element, a thin film diode, a photoelectric conversion elementcomprising a PIN junction of silicon and a silicon resistance element.3. A semiconductor device comprising a CMOS circuit disposed over aninsulating surface, said semiconductor device comprising: an N-channeltype TFT having a first semiconductor layer as an active layer, aninsulating film over said first semiconductor layer; a P-channel typeTFT having a second semiconductor layer as a active layer over theinsulating film, wherein said N-channel type TFT and said P-channel typeTFT are connected complementally to each other, only said insulatingfilm is provided between said first semiconductor layer and said secondsemiconductor layer, a gate insulating film of said P-channel type TFTand a gate electrode are provided over said semiconductor layer, a gateinsulating film of said N-channel type TFT and a gate electrode areprovided under said first semiconductor layer, a part of said firstsemiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween.4. A semiconductor device comprising a CMOS circuit disposed over aninsulating surface, said semiconductor device comprising: an P-channeltype TFT having a first semiconductor layer as an active layer, and aninsulating film over said first semiconductor layer; a N-channel typeTFT having a second semiconductor layer as a active layer over theinsulating film, wherein said P-channel type TFT and said N-channel typeTFT are connected complementally to each other, only said insulatingfilm is provided between said first semiconductor layer and said secondsemiconductor layer, above said second semiconductor layer, a gateinsulating film of said N-channel type TFT and a gate electrode areprovided over said second semiconductor layer, a gate insulating film ofsaid P-channel type TFT and a gate electrode are provided under saidfirst semiconductor layer, a part of said first semiconductor layer isoverlapped with a part of said second semiconductor layer with saidinsulating film sandwiched therebetween.
 5. A semiconductor devicecomprising an organic light emitting device disposed over an insulatingsurface, said semiconductor device comprising: an N-channel type TFThaving a first semiconductor layer as an active layer, an insulatingfilm over said first semiconductor layer; a P-channel type TFT having asecond semiconductor layer as a active layer over the insulating film,said P-channel type TFT is connected to the organic light emittingdevice, only said insulating film is provided between said firstsemiconductor layer and said second semiconductor layer, a gateinsulating film of said P-channel type TFT and a gate electrode areprovided over said second semiconductor layer, below said firstsemiconductor layer, a gate insulating film of said N-channel type TFTand a gate electrode are provided under said first semiconductor layer,a part of said first semiconductor layer is overlapped with a part ofsaid second semiconductor layer with said insulating film sandwichedtherebetween.
 6. A semiconductor device comprising a CMOS circuitdisposed on an insulated surface, wherein an N-channel type TFT having afirst semiconductor layer as an active layer, an insulating film on saidfirst semiconductor layer and a P-channel type TFT having a secondsemiconductor layer as a active layer on the insulating film areconnected complementally to each other, between said first semiconductorlayer and said second semiconductor layer, said insulating film only isincluded, above said second semiconductor layer, a gate insulating filmand a gate electrode are included, said gate electrode of said N-channeltype TFT and said P-channel type TFT is the identical, a part of saidfirst semiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween.7. A device according to claim 3, wherein the area where a part of saidfirst semiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween isa channel forming area.
 8. A device according to claim 3, wherein thearea where a part of said first semiconductor layer is overlapped with apart of said second semiconductor layer with said insulating filmsandwiched therebetween is a source area or drain area.
 9. A deviceaccording to claim 4, wherein the area where a part of said firstsemiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween isa channel forming area.
 10. A device according to claim 4, wherein thearea where a part of said first semiconductor layer is overlapped with apart of said second semiconductor layer with said insulating filmsandwiched therebetween is a source area or drain area.
 11. A deviceaccording to claim 5, wherein the area where a part of said firstsemiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween isa channel forming area.
 12. A device according to claim 5, wherein thearea where a part of said first semiconductor layer is overlapped with apart of said second semiconductor layer with said insulating filmsandwiched therebetween is a source area or drain area.
 13. A deviceaccording to claim 6, wherein the area where a part of said firstsemiconductor layer is overlapped with a part of said secondsemiconductor layer with said insulating film sandwiched therebetween isa channel forming area.
 14. A device according to claim 6, wherein thearea where a part of said first semiconductor layer is overlapped with apart of said second semiconductor layer with said insulating filmsandwiched therebetween is a source area or drain area.
 15. Asemiconductor device comprising a TFT having a plurality of channelforming areas disposed on an insulated surface, wherein the TFT includesa first semiconductor layer and a second semiconductor layer as activelayers, said first semiconductor layer and said second semiconductorlayer are electrically connected to each other via electrodes, betweensaid first semiconductor layer and said second semiconductor layer, aninsulating film only is included, on said second semiconductor layer, agate insulating film of the TFT, and on the gate insulating film, a gateelectrode are included, in said second semiconductor layer, an areawhere is overlapped with said gate electrode with said gate insulatingfilm sandwiched therebetween is a second channel forming area, in saidfirst semiconductor layer, an area where is overlapped with said gateelectrode with said gate insulating film, said second channel formingarea and said insulating film sandwiched therebetween is a first channelforming area.
 16. A device according to claim 3, wherein said firstsemiconductor layer and said second semiconductor layer aresemiconductor films having a crystal structure respectively.
 17. Adevice according to claim 4, wherein said first semiconductor layer andsaid second semiconductor layer are semiconductor films having a crystalstructure respectively.
 18. A device according to claim 5, wherein saidfirst semiconductor layer and said second semiconductor layer aresemiconductor films having a crystal structure respectively.
 19. Adevice according to claim 6, wherein said first semiconductor layer andsaid second semiconductor layer are semiconductor films having a crystalstructure respectively.
 20. A device according to claim 15, wherein saidfirst semiconductor layer and said second semiconductor layer aresemiconductor films having a crystal structure respectively.
 21. Adevice according to claim 3, wherein the channel length of the channelforming area in said first semiconductor layer and the channel length ofthe channel forming area in said second semiconductor layer are thesame.
 22. A device according to claim 4, wherein the channel length ofthe channel forming area in said first semiconductor layer and thechannel length of the channel forming area in said second semiconductorlayer are the same.
 23. A device according to claim 5, wherein thechannel length of the channel forming area in said first semiconductorlayer and the channel length of the channel forming area in said secondsemiconductor layer are the same.
 24. A device according to claim 6,wherein the channel length of the channel forming area in said firstsemiconductor layer and the channel length of the channel forming areain said second semiconductor layer are the same.
 25. A device accordingto claim 15, wherein the channel length of the channel forming area insaid first semiconductor layer and the channel length of the channelforming area in said second semiconductor layer are the same.
 26. Adevice according to claim 1, wherein the film thickness of said firstsemiconductor layer is the same as that of said second semiconductorlayer, or thinner than the film thickness of said second semiconductorlayer.
 27. A device according to claim 2, wherein the film thickness ofsaid first semiconductor layer is the same as that of said secondsemiconductor layer, or thinner than the film thickness of said secondsemiconductor layer.
 28. A device according to claim 3, wherein the filmthickness of said first semiconductor layer is the same as that of saidsecond semiconductor layer, or thinner than the film thickness of saidsecond semiconductor layer.
 29. A device according to claim 4, whereinthe film thickness of said first semiconductor layer is the same as thatof said second semiconductor layer, or thinner than the film thicknessof said second semiconductor layer.
 30. A device according to claim 5,wherein the film thickness of said first semiconductor layer is the sameas that of said second semiconductor layer, or thinner than the filmthickness of said second semiconductor layer.
 31. A device according toclaim 6, wherein the film thickness of said first semiconductor layer isthe same as that of said second semiconductor layer, or thinner than thefilm thickness of said second semiconductor layer.
 32. A deviceaccording to claim 15, wherein the film thickness of said firstsemiconductor layer is the same as that of said second semiconductorlayer, or thinner than the film thickness of said second semiconductorlayer.
 33. A manufacturing method of semiconductor device, comprising:forming a first semiconductor film having amorphous structure over aninsulating surface, forming an insulating film over the semiconductorfilm, forming a second semiconductor film having amorphous structureover the insulating film, irradiating a laser beam to said firstsemiconductor film having amorphous structure and said secondsemiconductor film having amorphous structure to form a firstsemiconductor film having crystal structure and a second semiconductorfilm having crystal structure simultaneously.
 34. A method according toclaim 33, wherein said laser beam is a light having a wavelength rangeof 400 nm-800 nm.
 35. A method according to claim 33, wherein said laserbeam is light output from a continuous oscillation type solid-statelaser.
 36. A method according to claim 33, wherein in the irradiation ofsaid laser beam, a part of said laser beam passes through said firstsemiconductor film having amorphous structure, and further passesthrough said insulating film and is absorbed by said secondsemiconductor film having amorphous structure.
 37. A method according toclaim 33, wherein in the irradiation of said laser beam, a part of saidlaser beam is reflected by the second semiconductor film havingamorphous structure, and is irradiated to said first semiconductor filmhaving amorphous structure.
 38. A method according to claim 33, whereinin the irradiation of said laser beam, a part of said laser beam repeatsthe reflection between said first semiconductor film having amorphousstructure and the second semiconductor film having amorphous structure,and is absorbed by the either one thereof.
 39. A method according toclaim 33, wherein in the irradiation of said laser beam, the energy ofthe laser beam absorbed by the first semiconductor film having amorphousstructure and the energy of the laser beam absorbed by the secondsemiconductor film having amorphous structure are the same.
 40. A methodaccording to claim 33, wherein in the irradiation of said laser beam,the energy of the laser beam absorbed by the first semiconductor filmhaving amorphous structure is made to be different from the energy ofthe laser beam absorbed by the second semiconductor film havingamorphous structure.
 41. A manufacturing method of semiconductor device,comprising: forming a first semiconductor film having amorphousstructure over an insulating surface, forming an first insulating filmover the semiconductor film, forming a second semiconductor film havingamorphous structure over the first insulating film, irradiating a laserbeam to said second semiconductor film having amorphous structure byallowing the same to pass through said first semiconductor film havingamorphous structure and said first insulating film to form a firstsemiconductor film having crystal structure and a second semiconductorfilm having crystal structure simultaneously, forming a secondinsulating film over the second semiconductor film having crystalstructure, forming a gate electrode over said second insulating film,adding an impurity element for imparting N-type or P-type to said firstsemiconductor film having crystal structure or said second semiconductorfilm having crystal structure using said gate electrode as a mask.
 42. Amanufacturing method of semiconductor device, comprising: forming afirst gate electrode over an insulating surface, forming a firstinsulating film for covering said first gate electrode, forming a firstsemiconductor film having amorphous structure over said first insulatingfilm, forming a second insulating film over the semiconductor film,forming a second semiconductor film having amorphous structure over thesecond insulating film, irradiating a laser beam to said secondsemiconductor film having amorphous structure by allowing the same topass through said first semiconductor film having amorphous structureand said second insulating film to form a first semiconductor filmhaving crystal structure and a second semiconductor film having crystalstructure simultaneously, forming a third insulating film over thesecond semiconductor film having crystal structure, forming a secondgate electrode over said third insulating film, adding an impurityelement for imparting N-type or P-type to said first semiconductor filmhaving crystal structure or said second semiconductor film havingcrystal structure using said second gate electrode as a mask.
 43. Amethod according to claim 42, wherein said first gate electrode is usedas the gate electrode of a TFT in which said first semiconductor filmhaving crystal structure is used as the active layer, said second gateelectrode is used as the gate electrode of a TFT in which said secondsemiconductor film having crystal structure is used as the active layer.44. A manufacturing method of semiconductor device, comprising:irradiating a laser beam to a first semiconductor film having amorphousstructure or crystal structure disposed over an insulating surface, aninsulating film over the semiconductor film and a second semiconductorfilm having amorphous structure or crystal structure over the insulatingfilm; and annealing said first semiconductor film and said secondsemiconductor film simultaneously.